https://github.com/zachjs/sv2v

SystemVerilog to Verilog conversion
https://github.com/zachjs/sv2v

conversion systemverilog verilog yosys

Last synced: 3 months ago
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SystemVerilog to Verilog conversion

• Host: GitHub
• URL: https://github.com/zachjs/sv2v
• Owner: zachjs
• License: bsd-3-clause
• Created: 2019-02-08T04:49:52.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2024-03-11T18:34:41.000Z (10 months ago)
• Last Synced: 2024-03-22T07:33:48.006Z (10 months ago)
• Topics: conversion, systemverilog, verilog, yosys
• Language: Haskell
• Homepage:
• Size: 1.71 MB
• Stars: 454
• Watchers: 13
• Forks: 48
• Open Issues: 17
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE

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