https://github.com/zazi2002/computer-architectur-lab
Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.
https://github.com/zazi2002/computer-architectur-lab
counter mips multicycle-processor pic32 verilog
Last synced: 3 months ago
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Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.
- Host: GitHub
- URL: https://github.com/zazi2002/computer-architectur-lab
- Owner: ZaZi2002
- Created: 2024-09-07T10:10:03.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2024-09-07T17:20:51.000Z (almost 2 years ago)
- Last Synced: 2024-12-28T10:44:35.979Z (over 1 year ago)
- Topics: counter, mips, multicycle-processor, pic32, verilog
- Language: Verilog
- Homepage:
- Size: 10.7 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Computer Architecture Lab
This repository contains code and simulations related to the Computer Architecture course. It covers the implementation of various fundamental computer architecture concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.
## Repository Structure
### 1. Multi-Cycle MIPS
This section contains Verilog code for a multi-cycle implementation of the MIPS processor. The design includes several key components:
- Instruction Fetch
- Instruction Decode
- Execution, Memory Access, and Write-Back
These components are combined to simulate the full functionality of a MIPS CPU using multiple clock cycles per instruction.
### 2. PIC32 Microcontroller
This section includes various PIC32 microcontroller codes, focusing on:
- Basic I/O control
- Peripheral programming
- Interrupt handling
- Timers and counters
These examples demonstrate programming techniques and hardware interaction with the PIC32 architecture.
## Requirements
Verilog simulator for MIPS.
MPLAB X IDE and XC32 Compiler for PIC32 microcontroller development.