https://github.com/zbreit/uart-verilog

A UART transmitter and receiver written in Verilog
https://github.com/zbreit/uart-verilog

Last synced: 18 days ago
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A UART transmitter and receiver written in Verilog

• Host: GitHub
• URL: https://github.com/zbreit/uart-verilog
• Owner: zbreit
• Created: 2021-05-02T20:32:20.000Z (over 3 years ago)
• Default Branch: main
• Last Pushed: 2021-05-10T02:25:21.000Z (over 3 years ago)
• Last Synced: 2023-04-29T08:29:37.255Z (over 1 year ago)
• Language: Verilog
• Size: 1.67 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

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