https://github.com/zegervdv/bitslice
Verilog bit slicing for python
https://github.com/zegervdv/bitslice
Last synced: 4 months ago
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Verilog bit slicing for python
- Host: GitHub
- URL: https://github.com/zegervdv/bitslice
- Owner: zegervdv
- License: mit
- Created: 2020-04-24T21:55:45.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2021-05-13T08:46:35.000Z (about 5 years ago)
- Last Synced: 2025-06-07T22:07:15.514Z (about 1 year ago)
- Language: Python
- Size: 35.2 KB
- Stars: 9
- Watchers: 3
- Forks: 4
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Bitslice
Verilog-like bitslicing for Python.
## Installation
Install the library from PyPI:
~~~
pip install bitslice
~~~
## Quickstart
Bitslice is designed to behave as an integer value as much as possible.
All operators defined on `int` should be supported.
Bitslice objects use indexing to emulate Verilog-style bit slicing.
~~~ python
from bitslice import Bitslice
value = Bitslice(5, size=4)
# Binary: 0b0101
print(value)
0x0005 (5)
# Select the lowest bit (index 0, right-most)
#
# index: 3210
# value: 0b0101
print(value[0])
0x0001 (1)
# Select bits 2 -> 1
# resulting in 0b10 == 2
print(value[2:1])
0x0002 (2)
# Set the upper bit
value[3] = 1
# 0b1101
print(value)
0x000D (13)
~~~
Advanced features: slice aliasing
~~~ python
value = Bitslice(5, size=4)
value.add_alias('lower', start=0, end=1)
value.add_alias('upper', start=2, end=3)
value['lower'] == value[1:0]
~~~
See [bitslice.py](https://github.com/zegervdv/bitslice/blob/master/bitslice/bitslice.py) for more examples.