https://github.com/zhijian-liu/mips-cpu
A toy CPU with five-stage MIPS pipeline
https://github.com/zhijian-liu/mips-cpu
mips-instructions pipeline-cpu verilog-hdl
Last synced: about 2 months ago
JSON representation
A toy CPU with five-stage MIPS pipeline
- Host: GitHub
- URL: https://github.com/zhijian-liu/mips-cpu
- Owner: zhijian-liu
- License: mit
- Created: 2016-09-06T08:39:57.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2017-11-28T23:43:25.000Z (over 7 years ago)
- Last Synced: 2023-03-03T01:34:04.880Z (about 2 years ago)
- Topics: mips-instructions, pipeline-cpu, verilog-hdl
- Language: Verilog
- Homepage:
- Size: 4.67 MB
- Stars: 5
- Watchers: 1
- Forks: 0
- Open Issues: 0