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https://github.com/zhixian001/snu430.322-public

Last synced: 8 days ago
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Host: GitHub
URL: https://github.com/zhixian001/snu430.322-public
Owner: zhixian001
Created: 2020-01-06T15:17:19.000Z (almost 5 years ago)
Default Branch: master
Last Pushed: 2020-01-06T15:17:42.000Z (almost 5 years ago)
Last Synced: 2023-10-10T12:28:21.045Z (about 1 year ago)
Language: Verilog
Size: 3.95 MB
Stars: 0
Watchers: 1
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: README.md

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README

        # SNU430.322 (19-spring)

SNU430.322 (19-spring) _Computer Organization_ class _verilog_ homeworks

## Tools needed

- VSCode

  - extensions 

    - mshr-h.veriloghdl

    - (optional) ericsonj.verilogformat

    - (optional) jaimeolivares.yuml

- [Icarus Verilog](http://iverilog.icarus.com/)

  - note: Please use iverilog with linux or WSL. Windows version doesn't work on some projects.

- [Xilinx Vivado](https://www.xilinx.com/products/design-tools/vivado.html)

## Workflow

`TODO`