https://github.com/zignig/patina

minimal riscv rust runtime for a FPGA core
https://github.com/zignig/patina

Last synced: 8 months ago
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minimal riscv rust runtime for a FPGA core

• Host: GitHub
• URL: https://github.com/zignig/patina
• Owner: zignig
• Created: 2023-10-23T12:57:38.000Z (over 2 years ago)
• Default Branch: main
• Last Pushed: 2025-03-22T07:45:14.000Z (about 1 year ago)
• Last Synced: 2025-09-10T21:53:39.447Z (9 months ago)
• Language: Python
• Homepage:
• Size: 693 KB
• Stars: 1
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

• amaranth-awesome - patina - V FPGA control plane development. (Uncategorized / Uncategorized)

README

          
# Minimal RISCV runtime

build environment for riscv32i on (https://github.com/cbiffle/hapenny)

An attempt at a minimal rust riscv framework for fpga control plane development 

# Overview 

# Installation

This project uses pdm so running `pdm install` should install all the python packages that are needed.

For the bootloader and the firmware a rust install for riscv32i-unknown-none-elf. 

# on the rust side

$ cargo install cargo-binutils

$ cargo install cargo-bloat

$ rustup component add llvm-tools

# pdm entry

to enter the PDM venv from the command line 

eval $(pdm venv activate in-project)

. .env.toolchain