https://github.com/zsh811/vhdl-digital-clock-system
A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.
https://github.com/zsh811/vhdl-digital-clock-system
digital-clock intel-quartus-prime modelsim vhdl
Last synced: 5 months ago
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A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.
- Host: GitHub
- URL: https://github.com/zsh811/vhdl-digital-clock-system
- Owner: zsh811
- Created: 2024-05-06T19:12:12.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2025-04-11T08:15:33.000Z (over 1 year ago)
- Last Synced: 2025-10-22T12:08:06.928Z (9 months ago)
- Topics: digital-clock, intel-quartus-prime, modelsim, vhdl
- Language: VHDL
- Homepage:
- Size: 16.6 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Digital Clock System
A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.
## Test Scenarios
1. _Testing the reset functionality_: When the reset signal is asserted, the clock's time components (seconds, minutes, and hours) are set to zero, ensuring a fresh start and providing a reliable baseline for timekeeping.
2. _Testing the seconds incrementation_: The testing of the seconds incrementation in the digital clock was successful, as observed in the waveform where the seconds component incremented correctly at each rising edge of the clock signal, validating its accurate timekeeping functionality.
3. _Testing the minutes incrementation_: It was observed that the minutes incremented correctly at each rising edge of the clock signal, after the second counter completed 59 counts, confirming the reliable functionality of the clock.
4. _Testing the hours Incrementation_: The observed waveform demonstrated that the hours were consistently incremented with precision reliably after the count of 59 minutes.
5. _Testing the reset after the 24 hour count_: By simulating the clock operation for a full 24-hour period and asserting the reset signal, the waveform was analyzed to ensure the clock properly reset to 1 and the rest of inputs and outputs to 0, allowing for seamless continuation of timekeeping beyond 24 hours.
