https://github.com/zxc479773533/HUST-Verilog-Labs

HUST Verilog Labs 2018 and Digital logic labs 2018
https://github.com/zxc479773533/HUST-Verilog-Labs

Last synced: 3 months ago
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HUST Verilog Labs 2018 and Digital logic labs 2018

• Host: GitHub
• URL: https://github.com/zxc479773533/HUST-Verilog-Labs
• Owner: zxc479773533
• License: mit
• Created: 2018-06-08T07:38:48.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-06-27T01:27:46.000Z (over 6 years ago)
• Last Synced: 2024-04-23T04:49:23.847Z (6 months ago)
• Language: Verilog
• Homepage:
• Size: 2.16 MB
• Stars: 18
• Watchers: 0
• Forks: 3
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-hust - zxc479773533

README

        
# HUST-Verilog-Labs

HUST Verilog Labs 2018

## Environment

* Arch Linux x86_64

* Visual Studio Code

* Vivado 2018.1

## About Labs

### Verilog labs

* lab01 - Vivado start

* lab02 - Simple combination circuit

* lab03 - Simple sequential circuit

* lab04 - FSM

* lab05 - Data path

### Digital logic labs

Some circuit design using logisim and vivado.