https://github.com/zyedidia/axum
A small SoC built around the Ibex processor
https://github.com/zyedidia/axum
Last synced: 7 months ago
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A small SoC built around the Ibex processor
- Host: GitHub
- URL: https://github.com/zyedidia/axum
- Owner: zyedidia
- Created: 2022-01-13T05:48:40.000Z (about 4 years ago)
- Default Branch: master
- Last Pushed: 2022-03-16T18:10:14.000Z (almost 4 years ago)
- Last Synced: 2025-06-05T00:52:24.279Z (7 months ago)
- Language: C
- Homepage:
- Size: 178 KB
- Stars: 2
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Axum
Axum is a small SoC built around the [Ibex](https://github.com/lowRISC/ibex)
RISC-V processor. It includes the processor itself, and a bus connecting GPIO,
timer, and UART devices. The build flow uses only open-source tooling and is
currently set up to target the open-source OrangeCrab ECP5-25F FPGA board. The
design can also be simulated using Verilator or Yosys CXXRTL.
The Ibex processor is configured in "small" mode, supporting RV32IMC, M-mode
and U-mode, and interrupts (primarily from the timer device).
The software uses the RISC-V GNU toolchain and includes a simple C library for
controlling the devices. This includes a minimal libc and printf support over
UART.
# Building
Make sure to initialize the Ibex submodule:
```
git submodule update --init
```
## Software
To build the software, you must have a RISC-V GNU toolchain installed. You must
also set the environment variable `LIBAXUM_ROOT` to point to the `sw/libaxum`
directory.
Navigate to the program you want to build in the `sw` directory and run
`make install`. This will place the generated bin file in `mem/` at the
project root.
## Hardware
First install the necessary tooling:
* sv2v (synthesis, simulation)
* Yosys (synthesis, simulation)
* Verilator (simulation)
* Project Trellis (ECP5 P&R and programming)
* GTKWave (view waveforms generated by simulation)
Select the appropriate mem file by editing `config.mk` or supplying the `MEM`
variable directly with the target.
Then you can make the following targets:
```sh
make verilator # outputs verilator simulation to obj_dir/sim.out.vtor
make cxxrtl # outputs CXXRTL simulation to sim/sim.out
make # outputs bitstream file for selected board
make prog # sends bitstream to FPGA (must be plugged in)
```
# Loading software
Once you compile a program to a RISC-V binary file, there are two ways of
loading it onto the FPGA. The first is to convert the binary file to a Verilog
memory file and place it in the `mem/` directory. Then specify the file in
`config.mk` or with `MEM=mem/file.vmem` when building the gateware. This will
build the program directly into the SRAM that is synthesized so that it will be
loaded immediately at start-up. However, this requires re-synthesizing the
design and loading new gateware even if you only change the software.
The other option is to use the software bootloader that is included with Axum.
First, synthesize the gateware with the memory file `mem/bootloader.vmem`.
Once this is uploaded to the FPGA, plug it in via a USB-UART connector. You can
then invoke the `axprog` program from `tools/` to send a program over UART. The
bootloader running at start-up will be waiting for a program to be sent, and
copy it into the SRAM and jump to it once the transfer is complete.