https://github.com/zyedidia/verilator-example
https://github.com/zyedidia/verilator-example
Last synced: 7 months ago
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- Host: GitHub
- URL: https://github.com/zyedidia/verilator-example
- Owner: zyedidia
- Created: 2022-01-30T21:30:09.000Z (almost 4 years ago)
- Default Branch: master
- Last Pushed: 2022-01-30T21:30:29.000Z (almost 4 years ago)
- Last Synced: 2025-03-05T23:25:44.497Z (10 months ago)
- Language: C++
- Size: 1.95 KB
- Stars: 1
- Watchers: 3
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
Compile the simulations with `make`, and then run with `./sim`. The simulations for `mux-trace` and `counter` generate a `trace.vcd` file. This can be inspected afterwards by running `gtkwave trace.vcd`. In gtkwave you can manually insert signals into the waveform (after opening the drop-down and selecting the module you want), or you can recursively import all signals (right click on the module you want).