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https://github.com/pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog

Last synced: 30 Jul 2024

https://github.com/OSVVM/AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

axi4 axi4-lite axi4-stream osvvm simulation simulation-modeling testbench tlm verification verification-component vhdl vip

Last synced: 30 Jul 2024