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https://github.com/chipsalliance/chisel

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 25 Jun 2024

https://github.com/ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar

Last synced: 24 Jun 2024