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Projects in Awesome Lists tagged with firrtl

A curated list of projects in awesome lists tagged with firrtl .

https://github.com/chipsalliance/chisel3

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 09 Nov 2024

https://github.com/chipsalliance/chisel

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 17 Dec 2024

https://github.com/chipsalliance/firrtl

Flexible Intermediate Representation for RTL

compiler firrtl hardware intermediate representation transformation

Last synced: 26 Oct 2024

https://github.com/ucsc-vama/essent

high-performance RTL simulator

chisel firrtl rtl scala

Last synced: 26 Oct 2024

https://github.com/freechipsproject/diagrammer

Provides dot visualizations of chisel/firrtl circuits

chisel chisel3 firrtl visualization

Last synced: 09 Nov 2024

https://github.com/grebe/ofdm

Chisel Things for OFDM

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 27 Oct 2024

https://github.com/thoughtworks/hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

chisel chisel3 firrtl floating-point fpu posit rtl scala unum verilog

Last synced: 09 Nov 2024

https://github.com/chipsalliance/tree-sitter-firrtl

FIRRTL grammar for tree-sitter

firrtl parser tree-sitter

Last synced: 13 Oct 2024