Projects in Awesome Lists tagged with fusesoc

A curated list of projects in awesome lists tagged with fusesoc .

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https://github.com/chipsalliance/cores-veer-eh1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 08 Feb 2026

https://github.com/chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 22 Apr 2025

https://github.com/chipsalliance/veerwolf

FuseSoC-based SoC for VeeR EH1 and EL2

fusesoc swerv tools veer

Last synced: 19 Feb 2026

https://github.com/chipsalliance/VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

fusesoc swerv tools veer

Last synced: 22 Jul 2025

https://github.com/chipsalliance/cores-veer-el2

VeeR EL2 Core

ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital

Last synced: 26 Jan 2026

https://github.com/chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital

Last synced: 02 Apr 2025

https://github.com/euripedesrocha/tbpp

A simple test library for verilator

cpp fusesoc verilator verilog

Last synced: 23 Mar 2025

https://github.com/josugoar/systemverilog-template

SystemVerilog FuseSoC template

fusesoc

Last synced: 15 May 2025

https://github.com/filmil/bazel_rules_fusesoc_2

Yet another attempt at bazel rules for fusesoc. This one relies on a hermetic installation of fusesoc and edalize, and not a containerized build. See https://github.com/filmil/bazel_rules_fusesoc for that other bit.

bazel bazel-rules eda fusesoc

Last synced: 26 May 2026