Projects in Awesome Lists tagged with rtl

https://github.com/youngsoft/mylinearlayout

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

android autolayout cocoapods constraints css3 flexbox-layout grid-layout ios layout layoutsubviews rtl sizeclasses storyboard ui uicollectionview uiscrollview uitableview view xcode xib

Last synced: 14 May 2025

https://github.com/youngsoft/MyLinearLayout

MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

android autolayout cocoapods constraints css3 flexbox-layout grid-layout ios layout layoutsubviews rtl sizeclasses storyboard ui uicollectionview uiscrollview uitableview view xcode xib

Last synced: 02 Aug 2025

https://github.com/chipsalliance/chisel

Chisel: A Modern Hardware Design Language

chip-generator chisel chisel3 firrtl rtl scala verilog

Last synced: 12 May 2025

https://github.com/chipsalliance/rocket-chip

Rocket Chip Generator

chip-generator chisel riscv rocket-chip rtl scala

Last synced: 17 Dec 2025

https://github.com/verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator

Last synced: 21 Feb 2026

https://github.com/layoutBox/PinLayout

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

anchor carthage chainable-methods cocoapod ios ios-lib ios-swift ios-ui language layout layout-engine left-language margin rtl swift swift-3 swift-framework swift-library uiview-extension

Last synced: 06 Aug 2025

https://github.com/layoutbox/pinlayout

Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

anchor carthage chainable-methods cocoapod ios ios-lib ios-swift ios-ui language layout layout-engine left-language margin rtl swift swift-3 swift-framework swift-library uiview-extension

Last synced: 11 Jun 2025

https://github.com/The-OpenROAD-Project/OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog

Last synced: 11 May 2025

https://github.com/riscv-boom/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

berkeley boom chisel riscv riscv-boom rocket-chip rtl scala

Last synced: 14 May 2025

https://github.com/the-openroad-project/openroad

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog

Last synced: 14 May 2025

https://github.com/ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar

Last synced: 14 May 2025

https://github.com/spinalhdl/spinalhdl

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 13 May 2025

https://github.com/SpinalHDL/SpinalHDL

Scala based HDL

fpga rtl scala verilog vhdl

Last synced: 15 Mar 2025

https://github.com/MohammadYounes/rtlcss

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

cascading-style-sheets css css3 flip i18n left-to-right ltr mirror postcss postcss-plugin right-to-left rtl rtlcss

Last synced: 05 Aug 2025

https://github.com/mohammadyounes/rtlcss

Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)

cascading-style-sheets css css3 flip i18n left-to-right ltr mirror postcss postcss-plugin right-to-left rtl rtlcss

Last synced: 14 May 2025

https://github.com/pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog

Last synced: 07 Mar 2026

https://github.com/the-openroad-project/openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Last synced: 14 May 2025

https://github.com/The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys

Last synced: 22 Apr 2025

https://github.com/siliconcompiler/siliconcompiler

Modular hardware build system

asic cmos eda fpga hls make rtl synthesis verilog vhdl

Last synced: 11 May 2026

https://github.com/kartik-v/bootstrap-star-rating

A simple yet powerful JQuery star rating plugin with fractional rating support.

bootstrap-star-rating caption change-stars css css-styles fractional javascript jquery rate-control rating rtl star star-symbols

Last synced: 14 May 2025

https://github.com/chipsalliance/cores-veer-eh1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 08 Feb 2026

https://github.com/veryl-lang/veryl

Veryl: A Modern Hardware Description Language

hdl rtl rust systemverilog verilog

Last synced: 04 Mar 2026

https://github.com/syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog

Last synced: 25 Mar 2025

https://github.com/eldraco/Salamandra

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

detect-microphones find-microphones microphone microphones python rtl salamandra sdr sound spy spy-microphones threshold

Last synced: 07 Apr 2025

https://github.com/chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 22 Apr 2025

https://github.com/adevintaspain/leku

:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

android android-library event-tracking geo-search geolocation geolocation-api google google-maps hacktoberfest kotlin kotlin-library library location location-picker maps multi-language place-picker placepicker rtl search-by-voice

Last synced: 04 Oct 2025

https://github.com/AdevintaSpain/Leku

:earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

android android-library event-tracking geo-search geolocation geolocation-api google google-maps hacktoberfest kotlin kotlin-library library location location-picker maps multi-language place-picker placepicker rtl search-by-voice

Last synced: 14 Mar 2025

https://github.com/ultraembedded/cores

Various HDL (Verilog) IP Cores

asic audio fpga i2s rtl sdram spi sram uart usb verilator verilog verilog-components verilog-hdl

Last synced: 25 Jan 2026

https://github.com/open-sdr/openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

ad9361 analog-devices csma dma fpga hardware hls ieee80211 linux mac80211 ofdm rtl sdr software-defined-radio verilog vhdl wi-fi xilinx zynq

Last synced: 15 May 2025

https://github.com/4xmen/web-package-rtl

⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷

4xmen components components-and-templates css full-package html persian persian-template right-to-left rtl rtl-component rtl-design rtl-package sass web-package xstack

Last synced: 14 Apr 2025

https://github.com/WangXuan95/FPGA-USB-Device

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

cdc fpga keyboard rtl usb usb-audio usb-camera usb-cdc usb-controller usb-device usb-disk usb-hid usb-keyboard usb-microphone usb-serial usb-speaker usb-uart usb-uvc uvc verilog

Last synced: 22 Apr 2025

https://github.com/seldridge/verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

fpga hardware rtl verilog

Last synced: 28 Jan 2026

https://github.com/ucb-bar/riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Last synced: 16 Mar 2025

https://github.com/fondesa/recycler-view-divider

A library which configures a divider for a RecyclerView.

android androidx divider divideritemdecoration gridlayoutmanager itemdecoration linearlayoutmanager list recyclerview rtl staggered staggeredgrid staggeredgridlayoutmanager

Last synced: 16 Jan 2026

https://github.com/the-openroad-project/openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog

Last synced: 22 Feb 2026

https://github.com/MahdiMajidzadeh/bootstrap-v4-rtl

RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic

arabic bootstrap css-framework farsi persian right-to-left rtl rtl-edition

Last synced: 11 May 2025

https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog

Last synced: 22 Jul 2025

https://github.com/pymtl/pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

cycle-level-modeling hardware-generation hdl multi-level-modeling open-source-eda open-source-hardware pymtl python rtl systemverilog verilog

Last synced: 04 Apr 2026

https://github.com/formwerkjs/formwerk

📝 The Vue.js framework for building tailored, accessible, and high-quality forms.

a11y accessibility design-system forms headless i18n internationalization rtl ui-components validation vue vue-components vue-composition-api

Last synced: 04 Mar 2026

https://github.com/Nuand/bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

80211 bladerf dsss hdl ofdm ofdm-wireless-communications rtl vhdl

Last synced: 25 Mar 2025

https://github.com/intel/rohd

The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

framework hardware hardware-design hardware-verification hdl rtl simulator verification

Last synced: 27 Dec 2025

https://github.com/20lives/tailwindcss-rtl

Enabling bidirectional support on tailwindcss framework

css direction logical ltr rtl tailwindcss tailwindcss-rtl

Last synced: 16 May 2025

https://github.com/WangXuan95/USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

cpu fpga risc-v riscv rtl rv32i soc softcore systemverilog verilog

Last synced: 22 Apr 2025

https://github.com/t0gre/react-datepicker

An easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.

datepicker grid i18n react react-hooks rtl styled-components styled-system typescript

Last synced: 05 Apr 2025

https://github.com/chipsalliance/sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

compliance-testing hdl rtl symbiflow systemverilog verilog

Last synced: 28 Jan 2026

https://github.com/bitbrain/jekyll-dash

🌒 Light and dark blog theme for Jekyll, inspired by Dash UI for Atom.

blog-theme dark-theme dash-ui github-pages jekyll jekyll-theme light-theme pagination right-to-left rtl ruby-gem rubygem syntax-highlighting tags theme

Last synced: 08 Apr 2025

https://github.com/tymonx/logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

asic cmake cpp fpga hdl modelsim quartus rtl systemc systemverilog testing-rtl unit-tests uvm verification verilator verilog vivado xilinx

Last synced: 14 Apr 2025

https://github.com/chipsalliance/cores-veer-el2

VeeR EL2 Core

ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital

Last synced: 26 Jan 2026

https://github.com/WangXuan95/FPGA-SDcard-Reader

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。

file-system fpga rtl sd-card sdcard sdio systemverilog verilog

Last synced: 22 Apr 2025

https://github.com/framevuerk/framevuerk

Fast, Responsive, Multi Language, Both Direction Support and Configurable UI Framework based on Vue.js.

configurable framework javascript js ltr multi-language multilanguage responsive rtl toolkit ui ux vue

Last synced: 16 Jul 2025

https://github.com/mortezakarimi/gentelella-rtl

Free RTL Bootstrap 3 Admin Template

admin-dashboard admin-template bootstrap-rtl bootstrap3 dashboard free gentelella-rtl html html-template jquery rtl

Last synced: 08 Apr 2025

https://github.com/rggen/rggen

Code generation tool for configuration and status registers

amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus

Last synced: 07 Jan 2026

https://github.com/chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital

Last synced: 02 Apr 2025

https://github.com/phphe/he-tree

Highly customizable draggable Vue.js tree component.

component drag-and-drop draggable rtl sortable table tree typescript virtuallist vue vue2 vue3

Last synced: 09 Oct 2025

https://github.com/ronmelkhior/tailwindcss-dir

Adds direction (LTR, RTL) variants to your Tailwind project

css left-to-right right-to-left rtl tailwind tailwindcss

Last synced: 12 Aug 2025

https://github.com/RonMelkhior/tailwindcss-dir

Adds direction (LTR, RTL) variants to your Tailwind project

css left-to-right right-to-left rtl tailwind tailwindcss

Last synced: 27 Mar 2025

https://github.com/abdelazeem201/systolic-array-implementation-in-rtl-for-tpu

IC implementation of Systolic Array for TPU

asic asic-design asic-verification fpga rtl verilog

Last synced: 28 Jan 2026

https://github.com/yifaneye/react-gallery-carousel

Carousel component 🎠🎠🎠 supporting touch, mouse, keyboard, thumbnails, fullscreen, lazy loading, SSR and customisations. 👉 Live editor: https://yifanai.com/rgcd1 👉 Example: https://koalaliving.com.au/Arya-Sand-Beige-Vegan-Leather-Dining-Chair

accessibility carousel component css dependency-free gallery html javascript lazy-loading lightbox mouse-emulation react reactjs responsive rtl slide slider swipe thumbnails touch

Last synced: 04 Apr 2025

https://github.com/nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: 08 Apr 2025

https://github.com/zetxek/adritian-free-hugo-theme

Adritian - High performance Hugo Theme for Personal Websites. With job experience, portfolio, dark/light theme, blog, multi-language and best frontend practices out of the box.

accessibility blog bootstrap dark-mode hacktoberfest hugo hugo-theme i18n landing-page multilingual personal-website portfolio responsive rtl seo static-site-generator theme website-template

Last synced: 28 Feb 2026

https://github.com/alanorth/hugo-theme-bootstrap4-blog

A blogging-centric Bootstrap v4 theme for the Hugo static site generator.

blog-theme bootstrap hugo hugo-theme i18n responsive-design rtl theme

Last synced: 09 Apr 2025

https://github.com/Nic30/hwt

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

codegen codegenerator compiler fpga hcl hls rtl simulator systemc systemverilog uvm verilog vhdl

Last synced: 15 Mar 2025

https://github.com/bu-icsg/dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

chisel hardware neural-network riscv rocc rocket-chip rtl

Last synced: 09 May 2025

https://github.com/airbnb/react-with-direction

Components to provide and consume RTL or LTR direction in React

directionality higher-order-component hoc left-to-right ltr provider react right-to-left rtl

Last synced: 04 Sep 2025

https://github.com/ucb-bar/constellation

A Chisel RTL generator for network-on-chip interconnects

chisel hardware interconnect network-on-chip noc rtl soc

Last synced: 04 Apr 2025

https://github.com/vkalinichev/postcss-rtl

PostCSS plugin for RTL-adaptivity

arabic css hebrew left-to-right postcss postcss-plugin postcss-rtl right-to-left rtl rtl-adaptivity rtlcss

Last synced: 08 Apr 2025

https://github.com/SpinalHDL/SaxonSoc

SoC based on VexRiscv and ICE40 UP5K

riscv rtl soc

Last synced: 22 Apr 2025

https://github.com/spinalhdl/saxonsoc

SoC based on VexRiscv and ICE40 UP5K

riscv rtl soc

Last synced: 05 Apr 2025

https://github.com/ics-jku/wal

WAL enables programmable waveform analysis.

eda hardware rtl verification

Last synced: 22 Jul 2025

https://github.com/renegadevi/nuxt-boilerplate

A ready to use Nuxt 3 boilerplate. (w/ HTTPS, Tailwind, i18n+RTL, Pinia, GDPR, Dark mode, TypeScript, Prettier, ESLint etc.)

cookies-consent dark-mode gdpr i18n lighthouse nuxt prettier prettier-eslint rtl tailwindcss

Last synced: 12 Jan 2026

https://github.com/zeroxme/bootstrap-3-arabic

bootstrap 3 arabic

bootstrap css less multilingual rtl

Last synced: 07 Apr 2026

https://github.com/ucsc-vama/essent

high-performance RTL simulator

chisel firrtl rtl scala

Last synced: 17 Jan 2026

https://github.com/ahmadajmi/markdown-arabic

Write Markdown in Arabic

arabic gulp javascript markdown rtl

Last synced: 30 Apr 2025

https://github.com/Guenael/rtlsdr-wsprd

WSPR daemon for RTL receivers

beacon c decoder propagation radio rtl rtl-sdr sdr wspr wsprnet

Last synced: 05 Apr 2025

https://github.com/ilhammeidi/veluxi-starter

Veluxi Vue.js Starter Project with Nuxt JS and Vuetify

animated-slider boilerplate carousel dark-theme i18n landing-page material-ui nuxt nuxtjs parallax rtl ssr starter-kit starter-project template vue vuejs vuejs2 vuetify vuetify-js

Last synced: 21 Aug 2025

https://github.com/perseusthegreat/bootstrap-4-rtl

Unofficial RTL-ized edition of Bootstrap 4.x

arabic bootstrap bootstrap-4 bootstrap-4-rtl bootstrap-rtl bootstrap4 bootstrap4-rtl css css-framework hebrew persian right-to-left rtl rtl-bootstrap scss scss-framework ui ui-ux uiux ux

Last synced: 01 Oct 2025

https://github.com/kamilmielnik/scrabble-solver

Free, open-source, cross-platform, multi-language analysis tool for Scrabble, Scrabble Duel, Super Scrabble, Letter League, Literaki, and Kelimelik. Quickly find the top-scoring words using the given board and tiles. Available in 8 languages.

crossword discord-letter-league kelimelik letter-league literaki literaxx next nextjs nodejs quackle react rtl scrabble scrabble-dictionary scrabble-duel scrabble-game scrabble-solver scrabble-word-finder solver super-scrabble

Last synced: 26 Apr 2026

https://github.com/dedidata/bootstrap-rtl

Bootstrap RTL Standard 3 and 4

arabic bootstrap bootstrap-rtl css hebrew persian responsive right-to-left rtl rtl-bootstrap

Last synced: 09 Apr 2025

https://github.com/dhogborg/rtl-gopow

Render tables from rtl_power to a nice heat map

heatmap rtl rtl-power rtl-sdr sdr

Last synced: 17 Mar 2025

https://github.com/elchininet/postcss-rtlcss

PostCSS plugin to automatically build Cascading Style Sheets (CSS) with Left-To-Right (LTR) and Right-To-Left (RTL) rules using RTLCSS

arabic automatic-ltr automatic-rtl css direction hebrew left-to-right ltr plugin postcss postcss-plugin postcss-rtlcss right-to-left rtl rtl-adaptivity rtl-plugin rtlcss

Last synced: 05 Apr 2025

https://github.com/michaelehab/aes-verilog

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

aes aes-128 aes-192 aes-256 aes-decryption aes-encryption cryptography encryption encryption-decryption fpga fpga-board fpga-soc learn rtl security verilog verilog-hdl verilog-project

Last synced: 08 Feb 2026

https://github.com/TheYahya/thewhite

:black_nib: It's a minimal and light wordpress blog theme :art:

farsi light minimal persian rtl theme timeline white wordpress wordpress-theme

Last synced: 15 May 2025

https://github.com/chili-chips-ba/opencologne

Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https://nanoxplore.com

colognechip design digital embedded fpga gatemate hls pcb risc-v rtl soc systemverilog

Last synced: 26 Jan 2026

https://github.com/MahdiMajidzadeh/materialize-rtl

RTL version of materializecss framework v1.0.0

css-framework material persian rtl

Last synced: 11 May 2025

https://github.com/WilsonChen003/HDLGen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

asic automation hdl perl python rtl script soc verilog

Last synced: 15 Mar 2025

https://github.com/PrincetonUniversity/AutoSVA

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

design methodology-development rtl sva systemverilog verification verilog

Last synced: 11 May 2025

https://github.com/ilhammeidi/awrora-starter

Landing page template built with one of most popular javascript library Vue.JS, Vuetify (Material Design) and Nuxt.JS with SSR.

dark-mode ecommerce i18n landing-page material-ui nuxt nuxtjs responsive rtl ssr starter-kit starter-project template translation vue vuejs vuetify wow-js

Last synced: 19 Apr 2025

https://github.com/ramezissac/django-tabular-permissions

Display Django permissions in a HTML table that is translatable and easily customized.

admin django permissions rtl translatable widget

Last synced: 18 Aug 2025

https://github.com/chili-chips-ba/wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

cocotb embedded fpga iss risc-v rtl verilator verilog vpn vproc wireguard

Last synced: 09 Apr 2025

https://github.com/querateam/mattermost-rtl

Adds RTL support to Mattermost

mattermost mattermost-plugin rtl

Last synced: 19 Oct 2025

https://github.com/princetonuniversity/autosva

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

design methodology-development rtl sva systemverilog verification verilog