Ecosyste.ms: Awesome

https://github.com/sgherbst/svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

fixed-point floating-point icarus icarus-verilog irun iverilog ncsim simulation synthesis synthesizable systemverilog vcs verilator verilog vivado xcelium xrun

Last synced: 03 Aug 2024

https://github.com/sgherbst/msdsl

Automatic generation of real number models from analog circuits

ams analog analog-circuits generator mixed-signal model python real-number-modeling rnm simulation synthesis synthesizable

Last synced: 03 Aug 2024

https://github.com/sgherbst/anasymod

A framework for FPGA emulation of mixed-signal systems

Last synced: 25 Oct 2024