Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
awesome-hwd-tools
A curated list of awesome open source hardware design tools
https://github.com/TM90/awesome-hwd-tools
- Nic30/hdlConverter - Python System-Verilog/VHDL Parser
- christiklein/simpy - discrite event based simulation framework
- chipmuenk/pyFDA - A python tool to design time discrete filters
- efabless/openlane - Automated RTL to GDS flow based on openRoad, Yosys and more...
- ahmed-agiza/EDAViewer - EDAV is a cloud-based open-source viewer for electronic design automation (EDA) design files (LEF, DEF)
- cornell-brg/pymtl3 - hardware modeling framework
- mortbopet/VSRTL - Visual Simulation of Register Transfer Logic
- freechipsproject/Chisel - Hardware Description Language embedded in Scala developed at UC Berkeley
- phanrahan/Magma - A Hardware Description Language embedded in Python
- llvm/circt - Intermediate representation for rtl (used by Chisel)
- myhdl/MyHDL - Python as a Hardware Description and Verification Language
- clash-lang/clash-compiler - A Hardware Description Language written and inspired by Haskell
- drom/awesome-hdl
- gtkwave - GTK based waveform viewer
- wavedrom/wavedrom - Timing Diagrams in Java Script
- steveicarus/iverilog - Icarus Verilog Simulator
- ghdl/ghdl - VHDL Simulator
- YosysHQ/yosys - Synthesis Flow
- abk-openroad/OpenSTA - static timing analysis
- OpenTimer/OpenTimer - timing analysis tool for vlsi systems
- YosysHQ/SymbiYosys - formal verification flow and tool
- cocotb/cocotb - Creating Verilog/VHDL testbenches with python
- leviathanch/libresiliconprocess - A 1um open process specification
- google/skywater-pdk - Open Source Process SkyWater 130nm
- heitzmann/gdspy - manipulating GDSII files in Python
- unihd-cag/skillbridge - A seamless python to Cadence Virtuoso Skill interface
- electronics-and-drives/SPAM - SPAM is a package management system for Cadence SKILL
- electronics-and-drives/ml2tikz - Virtuoso layout to tikzpicture
- MatthewLoveQUB/SKILL_Tools - Skill++ Tools including a test framework
- EDDRSoftware/oaFileParser - oaFile Parser
- scikit-rf/scikit-rf - RF and Microwave Design in scikit
- mph-/lcapy - Lcapy is a Python package for linear circuit analysis. It uses SymPy for symbolic mathematics.
- YosysHQ/PADRING - A padring generator for asics
- DegateCommunity/Degate - Tool for VLSI reverse engineering
- cap1tan/wafermap - A python package to plot maps of semiconductor wafers
- ucb-art/BAG_framework - Berkeley Analog Generator
- VLSIDA/OpenRAM - open-source SRAM Compiler
- KLayout/klayout - scriptable Layout Viewer and Editor
- ngspice - Spice Simulator
- FabriceSalvaire/pyspice - Simulating and creating Spice Circuits with Python
- Isotel/mixedsim - A mixed signal simulation approach using ngspice and yosys providing a library mapping to spice
- SchemDraw - producing circuit diagrams with python
Programming Languages
Keywords
python
7
verilog
6
vhdl
6
asic
5
eda
5
vlsi
4
virtuoso
3
cadence
3
hardware
3
skill
3
cadence-virtuoso
2
design-automation
2
llvm
2
magic
2
electronic-design-automation
2
cad
2
hardware-description-language
2
systemverilog
2
fpga
2
diagram
1
hdl
1
awesome-list
1
svg
1
compiler
1
gcc
1
ghdl
1
simulator
1
testbench
1
circuit-analysis
1
circuit-simulation
1
circuit-simulator
1
computer-aided-design
1
cpp17
1
antrl4
1
parser
1
systemverilog-parser
1
verilog-parser
1
vhdl-parser
1
cgo
1
def
1
def-viewer
1
digitaldesign
1
hardware-design
1
layout
1
lef
1
opendb
1
opendb-database
1
physical-synthesis
1
pixijs
1
server-side-rendering
1