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https://github.com/efabless/openlane
This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
https://github.com/efabless/openlane
Last synced: 2 months ago
JSON representation
This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
- Host: GitHub
- URL: https://github.com/efabless/openlane
- Owner: efabless
- License: apache-2.0
- Fork: true (The-OpenROAD-Project/OpenLane)
- Created: 2021-06-30T16:20:17.000Z (about 3 years ago)
- Default Branch: master
- Last Pushed: 2023-09-11T13:09:06.000Z (10 months ago)
- Last Synced: 2024-01-29T12:10:20.848Z (5 months ago)
- Language: Python
- Homepage: https://openlane.readthedocs.io/
- Size: 872 MB
- Stars: 125
- Watchers: 5
- Forks: 33
- Open Issues: 4
Lists
- awesome-hwd-tools - efabless/openlane - Automated RTL to GDS flow based on openRoad, Yosys and more... (Semi Custom Design/ FPGAs)
- awesome-sky130 - **openlane** - OpenLANE is an automated RTL to GDSII flow based on several components including [**OpenROAD**](https://github.com/The-OpenROAD-Project), [**Yosys**](http://www.clifford.at/yosys/), [**Magic**](http://opencircuitdesign.com/magic/), [**Netgen**](http://opencircuitdesign.com/netgen/), Fault, [**OpenPhySyn**](https://github.com/scale-lab/OpenPhySyn), [**CVC**](http://www.tachyon-da.com/what-is-cvc/), [**SPEF-Extractor**](https://github.com/HanyMoussa/SPEF_EXTRACTOR), [**CU-GR**](https://github.com/cuhk-eda/cu-gr), [**Klayout**](https://www.klayout.de/) and custom methodology scripts for design exploration and optimization (opensource tools)