Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
awesome-hdl
A curated list of awesome HDL, libraries, typical implementation and references.
https://github.com/fukatani/awesome-hdl
- Icarus Verilog - A Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
- verilog-mode - Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs.
- Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL.
- veriloggen - A library for constructing a Verilog HDL source code by Python.
- PyCoRAM - Python-based Portable IP-core Synthesis Framework for FPGA-based Computing.
- Pyverilog-toolbox - Pyverilog-based verification/design tool including code clone finder, metrics calculator and so on.
- miaow - An open source GPU based off of the AMD Southern Islands ISA.
- amiga2000-gfxcard - MNT VA2000, an Amiga 2000 Graphics Card (Zorro II), written in Verilog.
- gplgpu - GPL v3 2D/3D graphics engine in verilog.
- oh - Silicon validated Open Verilog library for IC and FPGA designers.
- FPGA-Litecoin-Miner - Litecoin script miner implemented with FPGA on-chip memory.
- verilog-ethernet - Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths).
- SystemVerilog Assertions Handbook - Assertion Guide for static and dynamic verification.
- Writing Testbenches using SystemVerilog - Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source.
- sublime-vhdl - VHDL Package for Sublime Text 2/3.
- nvc - VHDL compiler and simulator.
- vunit - A unit testing framework for VHDL/SystemVerilog.
- Open-Source-FPGA-Bitcoin-Miner - A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs.
- space-invaders-vhdl - Space Invaders game implemented with VHDL.
- IntroToSpartanFPGABook - A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards.
- EDA playground - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
- Asynchronous & Synchronous Reset Design Techniques
- Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Keywords
compiler
3
vhdl
3
fpga
3
hardware
3
verilog-hdl
3
python
2
emacs-lisp
1
systemverilog
1
verilog
1
verilog-mode
1
code-generator
1
control-flow-analyzer
1
dataflow-analyzer
1
parser
1
hardware-construction-language
1
high-level-synthesis
1
pyverilog
1
simulator
1
asic
1
systemverilog-hdl
1
testbench
1
unit-testing
1
universal-verification-methodology
1
verification
1
games
1