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awesome-riscv
😎 A curated list of awesome RISC-V implementations
https://github.com/drom/awesome-riscv
Last synced: 3 days ago
JSON representation
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Open Source implementations
- PicoRV32
- Ibex
- riscv-mini - bar/riscv-mini?label=★)
- Rocket - chip?label=★)
- SERV - calories|FPGA|ISC| ![](https://img.shields.io/github/stars/olofk/serv?label=★)
- VexRiscv - 5 stage|FPGA|MIT| ![](https://img.shields.io/github/stars/SpinalHDL/VexRiscv?label=★)
- wyvernSemi
- cva6
- CV32E40P
- FWRISC-S - s?label=★)
- NEORV32
- vroom - 2|ASIC|GPL3| ![](https://img.shields.io/github/stars/MoonbaseOtago/vroom?label=★)
- NaxRiscv
- CV32E40P
- Ibex
- riscv-mini - bar/riscv-mini?label=★)
- Rocket - chip?label=★)
- SERV - calories|FPGA|ISC| ![](https://img.shields.io/github/stars/olofk/serv?label=★)
- VexRiscv - 5 stage|FPGA|MIT| ![](https://img.shields.io/github/stars/SpinalHDL/VexRiscv?label=★)
- wyvernSemi
- NEORV32
- vroom - 2|ASIC|GPL3| ![](https://img.shields.io/github/stars/MoonbaseOtago/vroom?label=★)
- NaxRiscv
- Minerva
- SweRV - stage, dual-issue, superscalar|ASIC|Apache2| ![](https://img.shields.io/github/stars/chipsalliance/Cores-SweRV?label=★)
Programming Languages
Categories
Sub Categories
Keywords
riscv
10
risc-v
9
fpga
9
verilog
8
rtl
6
asic
5
cpu
5
vhdl
4
rv32
4
chisel
4
soc
4
soft-core
4
processor
4
32-bit
2
spinalhdl
2
softcore
2
scala
2
rocket-chip
2
chip-generator
2
hardware
2
cpucore
2
system-on-chip
2
safety
2
openocd
2
neorv32
2
microcontroller
2
gdb
2
embedded
2
asip
2
riscv32imfc
2
risc-processor
2
linux
2
iss
2
embedded-systems
2
cpu-model
2
co-simulation
2
c-plus-plus
2
systemverilog-hdl
1
rv64gc
1
ariane
1