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awesome-riscv

😎 A curated list of awesome RISC-V implementations
https://github.com/drom/awesome-riscv

Last synced: 3 days ago
JSON representation

  • Open Source implementations

    • PicoRV32
    • Ibex
    • riscv-mini - bar/riscv-mini?label=★)
    • Rocket - chip?label=★)
    • SERV - calories|FPGA|ISC| ![](https://img.shields.io/github/stars/olofk/serv?label=★)
    • VexRiscv - 5 stage|FPGA|MIT| ![](https://img.shields.io/github/stars/SpinalHDL/VexRiscv?label=★)
    • wyvernSemi
    • cva6
    • CV32E40P
    • FWRISC-S - s?label=★)
    • NEORV32
    • vroom - 2|ASIC|GPL3| ![](https://img.shields.io/github/stars/MoonbaseOtago/vroom?label=★)
    • NaxRiscv
    • CV32E40P
    • Ibex
    • riscv-mini - bar/riscv-mini?label=★)
    • Rocket - chip?label=★)
    • SERV - calories|FPGA|ISC| ![](https://img.shields.io/github/stars/olofk/serv?label=★)
    • VexRiscv - 5 stage|FPGA|MIT| ![](https://img.shields.io/github/stars/SpinalHDL/VexRiscv?label=★)
    • wyvernSemi
    • NEORV32
    • vroom - 2|ASIC|GPL3| ![](https://img.shields.io/github/stars/MoonbaseOtago/vroom?label=★)
    • NaxRiscv
    • Minerva
    • SweRV - stage, dual-issue, superscalar|ASIC|Apache2| ![](https://img.shields.io/github/stars/chipsalliance/Cores-SweRV?label=★)