https://github.com/SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
https://github.com/SpinalHDL/VexRiscv

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 14 days ago
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A FPGA friendly 32 bit RISC-V CPU implementation

• Host: GitHub
• URL: https://github.com/SpinalHDL/VexRiscv
• Owner: SpinalHDL
• License: mit
• Created: 2017-03-08T21:14:28.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2024-10-21T15:25:33.000Z (18 days ago)
• Last Synced: 2024-10-22T02:15:35.315Z (18 days ago)
• Topics: cpu, fpga, riscv, soc, softcore, spinalhdl, verilog, vhdl
• Language: Assembly
• Homepage:
• Size: 12.8 MB
• Stars: 2,474
• Watchers: 101
• Forks: 416
• Open Issues: 106
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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