awesome-RISCV-Cores

A curated list of spec, maturity comparison between current Open RISC-V cores.
https://github.com/yunchenlo/awesome-RISCV-Cores

Last synced: 3 days ago
JSON representation

Cores
- Industry
  - GitHub - draft | 2.3-draft | BSD | SiFive
  - GitHub
  - GitHub
  - GitHub - Commercial License | Roa Logic
  - GitHub
  - GitHub
  - GitHub
  - GitHub
  - GitHub
  - GitHub
  - GitHub
  - GitHub - draft | 2.3-draft | BSD | Esperanto, UCB Bar
  - GitHub
  - Website
- Academia
  - Website - platform/ariane) | | RV64IMC | Solderpad Hardware License v. 0.51 | ETH Zurich, Università di Bologna
  - Website - csg/riscy) | | | MIT | MIT CSAIL CSG
PPA Comparison
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link
- Link

Programming Languages

SystemVerilog 3 Verilog 3 Scala 2 Python 1 VHDL 1 Assembly 1

Categories

PPA Comparison 29 Cores 16 License 2

Sub Categories

Industry 14 Academia 4

Keywords

verilog 4 risc-v 4 cpu 3 fpga 2 riscv 2 core 2 rv32emc 1 rv32e 1 rtl 1 ip 1 rv32i 1 rv32imc 1 64bit 1 32-bit 1 vhdl 1 china 1 spinalhdl 1 softcore 1 soc 1 nuclei 1 ultra-low-power 1 asic 1