https://github.com/SI-RISCV/e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
https://github.com/SI-RISCV/e200_opensource

china core cpu nuclei risc-v ultra-low-power verilog

Last synced: 2 months ago
JSON representation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

• Host: GitHub
• URL: https://github.com/SI-RISCV/e200_opensource
• Owner: SI-RISCV
• License: apache-2.0
• Archived: true
• Created: 2017-07-27T15:38:44.000Z (almost 8 years ago)
• Default Branch: master
• Last Pushed: 2021-03-24T09:38:39.000Z (over 4 years ago)
• Last Synced: 2024-11-10T00:33:03.617Z (8 months ago)
• Topics: china, core, cpu, nuclei, risc-v, ultra-low-power, verilog
• Language: Verilog
• Homepage: https://github.com/riscv-mcu/e203_hbirdv2
• Size: 90.1 MB
• Stars: 2,629
• Watchers: 229
• Forks: 1,013
• Open Issues: 33
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-RISCV-Cores - GitHub
• StarryDivineSky - SI-RISCV/e200_opensource