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https://github.com/SI-RISCV/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
https://github.com/SI-RISCV/e200_opensource
china core cpu nuclei risc-v ultra-low-power verilog
Last synced: 3 months ago
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Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
- Host: GitHub
- URL: https://github.com/SI-RISCV/e200_opensource
- Owner: SI-RISCV
- License: apache-2.0
- Archived: true
- Created: 2017-07-27T15:38:44.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2021-03-24T09:38:39.000Z (over 3 years ago)
- Last Synced: 2024-06-15T23:35:56.062Z (5 months ago)
- Topics: china, core, cpu, nuclei, risc-v, ultra-low-power, verilog
- Language: Verilog
- Homepage: https://github.com/riscv-mcu/e203_hbirdv2
- Size: 90.1 MB
- Stars: 2,550
- Watchers: 229
- Forks: 994
- Open Issues: 33
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Metadata Files:
- Readme: README.md
- License: LICENSE
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- awesome-RISCV-Cores - GitHub
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