https://github.com/tomverbeure/mr1
MR1 formally verified RISC-V CPU
https://github.com/tomverbeure/mr1
Last synced: about 2 months ago
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MR1 formally verified RISC-V CPU
- Host: GitHub
- URL: https://github.com/tomverbeure/mr1
- Owner: tomverbeure
- License: unlicense
- Created: 2018-08-17T04:17:00.000Z (almost 7 years ago)
- Default Branch: master
- Last Pushed: 2018-12-16T19:42:59.000Z (over 6 years ago)
- Last Synced: 2025-03-31T17:58:53.853Z (3 months ago)
- Language: Scala
- Homepage: https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html
- Size: 119 KB
- Stars: 54
- Watchers: 1
- Forks: 6
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
- awesome-RISCV-Cores - GitHub
README
MR1
===
A hobby RISC-V CPU core to learn riscv-formal and SpinalHDL.
See my write-up here: [A Bug Free RISC-V Core without Simulation](https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html).
While this core works and has passed the riscv-formal test suite, it's not nearly as good as the
[VexRiscv](https://github.com/SpinalHDL/VexRiscv) core, which is smaller, synthesizes with higher clocks,
and has better IPC even in slow configurations.