https://github.com/yupferris/kaze

An HDL embedded in Rust.
https://github.com/yupferris/kaze

digital-logic-design hdl rust

Last synced: 3 months ago
JSON representation

An HDL embedded in Rust.

• Host: GitHub
• URL: https://github.com/yupferris/kaze
• Owner: yupferris
• License: apache-2.0
• Created: 2019-12-22T20:16:42.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2023-11-15T21:54:24.000Z (8 months ago)
• Last Synced: 2023-12-16T02:16:08.406Z (7 months ago)
• Topics: digital-logic-design, hdl, rust
• Language: Rust
• Homepage:
• Size: 319 KB
• Stars: 193
• Watchers: 14
• Forks: 9
• Open Issues: 31
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE-APACHE

Lists

• awesome-hdl - kaze - Meta HDL, 2019+ (Meta HDL and Transpilers)
• awesome-hdl - kaze - Meta HDL, 2019+ (Meta HDL and Transpilers)
• awesome-stars - yupferris/kaze - An HDL embedded in Rust. (Rust)
• awesome-cuda-tensorrt-fpga - yupferris/kaze

README

        
# kaze [風](https://jisho.org/search/%E9%A2%A8%20%23kanji)

An [HDL](https://en.wikipedia.org/wiki/Hardware_description_language) embedded in [Rust](https://www.rust-lang.org/).

[](https://github.com/yupferris/kaze)

[](https://crates.io/crates/kaze)

[](https://docs.rs/kaze)

[](#license)

kaze provides an API to describe `Module`s composed of `Signal`s, which can then be used to generate Rust simulator code or Verilog modules.

kaze's API is designed to be as minimal as possible while still being expressive.

It's designed to prevent the user from being able to describe buggy or incorrect hardware as much as possible.

This enables a user to hack on designs fearlessly, while the API and generators ensure that these designs are sound.

## Usage

```toml

[dependencies]

kaze = "0.1"

```

## Example

```rust

use kaze::*;

fn main() -> std::io::Result<()> {

    // Create a context, which will contain our module(s)

    let c = Context::new();

    // Create a module

    let inverter = c.module("Inverter");

    let i = inverter.input("i", 1); // 1-bit input

    inverter.output("o", !i); // Output inverted input

    // Generate Rust simulator code

    sim::generate(inverter, sim::GenerationOptions::default(), std::io::stdout())?;

    // Generate Verilog code

    verilog::generate(inverter, std::io::stdout())?;

    Ok(())

}

```

## Releases

See [changelog](https://github.com/yupferris/kaze/blob/master/CHANGELOG.md) for release information.

## License

Licensed under either of

 * Apache License, Version 2.0

   ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)

 * MIT license

   ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)

at your option.

## Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted

for inclusion in the work by you, as defined in the Apache-2.0 license, shall be

dual licensed as above, without any additional terms or conditions.