Ecosyste.ms: Awesome

An open API service indexing awesome lists of open source software.

awesome-hdl


https://github.com/bushbecky/awesome-hdl

  • IEEE Std 1364-2001 - hdl.com/pdfs/verilog_2001_ref_guide.pdf), [SystemVerilog 3.1a](http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf), [Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification](http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)
  • IEEE Std 1076-2000
  • IEEE Std 1666-2011
  • Verilator
  • Icarus Verilog - simulator
  • Yosys - RTL synthesis
  • nvc - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C
  • GHDL - VHDL compiler and simulator, IEEE 1076-2002, written in ADA
  • essent - firrtl to optimized C++ transpiler
  • treadle - firrtl simulator written in Scala
  • Lola-2
  • Oberon-2013 - Project Oberon, 2013 Edition, written in [Oberon-07](http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) [License](https://inf.ethz.ch/personal/wirth/ProjectOberon/license.txt)
  • SystemC - an IEEE standard meta-HDL
  • VisualHDL - an integrated development environment (IDE) rapid design for FPGAs
  • ROHD - A framework for hardware description and verification, 2021+
  • concat
  • CλaSH - A functional hardware description language
  • pipelineDSL - A Haskell DSL for describing hardware pipelines
  • Bluespec - Compiler, simulator, and tools for the Bluespec Hardware Description Language.
  • sv2v - SystemVerilog to Verilog conversion
  • jhdl
  • PSHDL
  • reqack - elastic circuit toolchain
  • hdl-js - Hardware description language (HDL) parser, and Hardware simulator.
  • shdl - Simple Hardware Description Language
  • Julia-Verilog - a Verilog-generation DSL for Julia., 2017
  • Hardcaml
  • Verik
  • HWT - core generator, analysis tools, HDL glue
  • garnet - Grained Reconfigurable Architecture generator based on magma, 2018+
  • magma - Meta HDL, 2017+
  • migen - Meta HDL, 2011+
  • MyHDL - Process based HDL, verification framework included, 2004+
  • nMigen - A refreshed Python toolbox for building complex digital hardware, 2018+
  • Pyrope - Python-like language supporting "fluid pipelines" and "live flow", 2017+
  • PyRTL - Meta HDL, simulator suitable for research.
  • PyMTL - Process based HDL, verification framework included, 2014+
  • veriloggen - Python, Verilog centric meta HDL with HLS like features, 2015-?
  • Hdl21 - Analog HDL in Python
  • RHDL
  • hoodlum - Meta HDL, 2016+
  • kaze - Meta HDL, 2019+
  • calyx - Intermediate Language (IL) for Hardware Accelerator Generators, 2020+
  • chisel - Meta HDL, 2012+
  • SpinalHDL - Meta HDL 2012+
  • Quokka - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)
  • Veryl - An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog
  • hlslibs - ac_math, ac_dsp, ac_types
  • legup - 2011-2015, LLVM based c->verilog
  • bambu - 2003-?, GCC based c->verilog
  • augh - c->verilog, DSP support
  • Shang - 2012-2014, LLVM based, c->verilog
  • xronos - 2012, java, simple HLS
  • Potholes - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET
  • hls_recurse - 2015-2016 - conversion of recursive fn. for stackless architectures
  • hg_lvl_syn - 2010, ILP, Force Directed scheduler
  • abc - ?, A System for Sequential Synthesis and Verification
  • polyphony - 2015-2017, simple python to hdl
  • DelayGraph - 2016, C#, register assignment algorithms
  • ahaHLS - 2019, An open source high level synthesis (HLS) tool using LLVM
  • combinatorylogic/soc - 2019, An experimental System-on-Chip with a custom compiler toolchain.
  • Quokka - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)
  • Vitis - LLVM based, made by Xilinx. [user manual](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf)
  • act - asynchronous circuit/compiler tools
  • autopiper
  • TL-Verilog - 2015+, Supports "timing-abstract" and "transaction-level design" methodologies; supported by proprietary and open-source tools
  • CIRCT - 2020+, LLVM / MLIR framework "Circuit IR Compilers and Tools"
  • coreir - 2016-?, LLVM HW compiler## License
  • lgraph - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design
  • firrtl - 2016-?, Flexible Intermediate Representation for RTL
  • LLHD - Low Level Hardware Description — A foundation for building hardware design tools
  • SpyDrNet - 2019+, Framework for parsing and manipulating structural netlists in Python
  • VLSIR - IC Interchange Formats, defined in Google Protobuf SDL
  • vtr-verilog-to-routing
  • yosys - RTL synthesis framework
  • bitfield - Javascript bit field diagram renderer
  • d3-wave - Javascript wave graph visualizer for RTL simulations
  • d3-hwschematic - Javascript hierarchical schematic visualizer for HDLs
  • wavedrom - Javascript wave graph visualizer for documentations and sim.
  • netlistsvg - Javascript schematic visualizer
  • sphinx-hwt - Plugin for sphinx documentation generator which adds schematic into html documentation.
  • Visual Debug - Custom simulation visualization framework, available within the [Makerchip.com](https://makerchip.com) IDE.
  • hdlConvertor - Fast (System) Verilog/VHDL parser written as C++ extension for Python
  • pyVHDLParser - VHDL parser written in Python
  • rust_hdl - VHDL parser and language server written in Rust
  • sv-parser - IEEE 1800-2017 System Verilog Parser written in Rust
  • verible - Verible provides a SystemVerilog parser, style-linter, and formatter.
  • midas - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  • cocotb - A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python
  • osvvm - A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow
  • RgGen - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications
  • sv-tests - Test suite designed to check compliance with the SystemVerilog standard
  • tbengy - Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs
  • HDLGen - Tool for processing of embedded Perl or Python scripts in Verilog source code.
  • ![CC0
  • Aliaksei Chapyzhenka
Programming Languages
Python 13 C++ 11 Rust 4 JavaScript 4 Haskell 4 Scala 4 Verilog 4 Ruby 2 VHDL 2 TypeScript 1
Keywords
verilog 11 vhdl 9 fpga 8 systemverilog 7 rtl 6 hdl 5 hardware 5 eda 4 parser 4 compiler 4 simulator 4 cad 3 hardware-description-language 3 python 3 asic 3 yosys 2 systemverilog-parser 2 verification 2 netlist 2 rust 2 circuit 2 scala 2 uvm 2 llvm 2 soc 2 digital-logic-design 1 asynchronous-circuits 1 asynchronous-vlsi 1 language-design 1 automation 1 verilog-hdl 1 chp 1 circuit-simulator 1 communicating-hardware-processes 1 dataflow 1 dataflow-programming 1 design-automation 1 language 1 production-rules 1 prs 1 vlsi 1 ghdl 1 gcc 1 testbench 1 chisel 1 firrtl 1 framework 1 hardware-design 1 hardware-verification 1 script 1