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https://github.com/Vlsir/Vlsir
Interchange formats for chip design.
https://github.com/Vlsir/Vlsir
Last synced: 3 months ago
JSON representation
Interchange formats for chip design.
- Host: GitHub
- URL: https://github.com/Vlsir/Vlsir
- Owner: Vlsir
- License: bsd-3-clause
- Created: 2021-12-17T01:44:31.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2023-11-14T19:04:59.000Z (8 months ago)
- Last Synced: 2024-01-14T22:53:01.095Z (6 months ago)
- Language: Python
- Size: 1.69 MB
- Stars: 18
- Watchers: 3
- Forks: 9
- Open Issues: 24
-
Metadata Files:
- Readme: readme.md
- License: LICENSE
Lists
- awesome-hdl - VLSIR - IC Interchange Formats, defined in Google Protobuf SDL (Hardware Intermediate Representations)
- awesome-opensource-hardware - vlsir
- awesome-hdl - VLSIR - IC Interchange Formats, defined in Google Protobuf SDL (Hardware Intermediate Representations)
README
# Vlsir
Interchange formats for chip design.
---
Vlsir defines data schema for integrated circuit (IC) circuits, layouts, and simulations,
using Google's [Protocol Buffer](https://developers.google.com/protocol-buffers/) schema definition language.
The name _Vlsir_ is a merger of _VLSI_ (very large scale integration - a way-outdated chip-world acronym)
and _IR_ (intermediate representation - the term every cool-kid copying compiler designers uses nowadays).
## Contents
All of Vlsir's schema-definitions live in the [protos](./protos) directory.
| Schema | Description |
| -------------------------------------- | ------------------------------- |
| [Circuit](https://github.com/Vlsir/schema-proto/blob/main/circuit.proto) | Circuit / Hardware Descriptions |
| [Raw Layout](https://github.com/Vlsir/schema-proto/blob/main/layout/raw.proto) | "Raw Polygon" IC Layout |
| [Tetris Layout](https://github.com/Vlsir/schema-proto/blob/main/layout/tetris.proto) | "Tetris" Gridded IC Layout |
| [Spice](https://github.com/Vlsir/schema-proto/blob/main/spice.proto) | Spice-Class Simulator Interface |
| [Utilities](https://github.com/Vlsir/schema-proto/blob/main/utils.proto) | Shared Utilities |
## Language Bindings
_Vlsir_ defines a [data schema](https://github.com/Vlsir/schema-proto), which related projects use in code.
Projects using _vlsir_ can be written in any language with protobuf-compiler bindings -
which includes essentially every popular programming language.
Existing projects have prominently used Python, C++, and Rust. In this repository we have supported bindings
for Python and Rust which can be found in `bindings` and downloaded from their respective package managers:
| Language | Bindings Package | Compiler |
| -------- | ---------------- | -------- |
| Python | https://pypi.org/project/vlsir/ | Google `protoc` |
| Rust | https://crates.io/crates/vlsir | [Prost](https://github.com/tokio-rs/prost) |
## Vlsir Tools
The `Vlsir` repository also serves as home for the Python-language [VlsirTools](https://pypi.org/project/vlsirtools/) package.
`VlsirTools` is a collection of tools for working with Vlsir's schema, including:
* Netlisting to industry-standard formats (SPICE, Verilog, etc.)
* Drivers and result-parsers for Spice-class simulators
## Building
The repository includes build scripts for Python, Rust, C++, Javascript and Julia bindings, of which only Rust and Python are actively maintained and tested. These can all be built individually with `scripts/build_.sh` or with either of the two joint scripts:
- `build_supported.sh`, this builds all supported bindings for use by Vlsir developers
- `build_all_recipes.sh`, this builds all bindings and is primarily used for testing
To build, run the script below:
```
git clone [email protected]:Vlsir/Vlsir
cd Vlsir
scripts/build_.sh
```
## Projects
Ongoing, co-developed projects which use `vlsir`:
| Project | Description | Language |
| -------- | ----------- | -------- |
| [Hdl21](https://github.com/dan-fritchman/Hdl21) | Generator-Based Hardware Description Library | Python |
| [Layout21](https://github.com/dan-fritchman/Layout21) | Multi-Layered Layout-Programming | Rust |
| [BFG](https://github.com/growly/bfg) | Layout Generation for Open-Source FPGAs | C++ |