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https://github.com/rdaly525/coreir

c-plus-plus compilers coreir hardware intermediate-representation llvm

Last synced: 7 days ago
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Host: GitHub
URL: https://github.com/rdaly525/coreir
Owner: rdaly525
License: bsd-3-clause
Created: 2016-10-24T06:15:23.000Z (over 7 years ago)
Default Branch: master
Last Pushed: 2022-06-27T21:42:15.000Z (about 2 years ago)
Last Synced: 2024-04-23T13:06:03.380Z (2 months ago)
Topics: c-plus-plus, compilers, coreir, hardware, intermediate-representation, llvm
Language: C++
Size: 7.22 MB
Stars: 96
Watchers: 14
Forks: 24
Open Issues: 156
Metadata Files:
- Readme: README.md
- License: LICENSE.txt

Lists

awesome-hdl - coreir - 2016-?, LLVM HW compiler## License (Hardware Intermediate Representations)
awesome-opensource-hardware - coreir
awesome-hdl - coreir - 2016-?, LLVM HW compiler## License (Hardware Intermediate Representations)

README

        [![Build Status](https://travis-ci.org/rdaly525/coreir.svg?branch=master)](https://travis-ci.org/rdaly525/coreir)

## CoreIR

  An LLVM-style hardware compiler with first class support for generators

## Installation Instructions

  Found [here](INSTALL.md)

## License

  CoreIR is open source under the terms of the freeBSD license found in this [license file](LICENSE.txt)

## Documentation

### Documentation for Users

  * This [document](doc/Standalone.md) describes the standalone coreir tool (similar to LLVM's 'opt')

  * This is the [specification](doc/JsonSpec.md) for the CoreIR serialization format (hardware object file)

  * This is a [specification](doc/coreirprims.csv) of CoreIR Primitives and Primitive Extentions

### Documentation for Developers

  * This [Getting Started Guide](doc/GettingStarted.md) provides an introduction and in depth look at how to use the CoreIR C++ API

  * This [Compilation Passes Guide](doc/WritingPasses.md) describes the process of creating new compilation passes

  * This [Library Guide](doc/LibraryGuide.md) talks about creating standalone CoreIR compatible Libraries

  * This [Guide](doc/Simulator.md) describes how to simulate CoreIR hardware graphs

  * This [Style Guide](doc/Style.md) discusses expected coding style for CoreIR

## Bugs and Feature Requests

Please submit an issue through github