https://github.com/rggen/rggen

Code generation tool for configuration and status registers
https://github.com/rggen/rggen

amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus

Last synced: 3 months ago
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Code generation tool for configuration and status registers

• Host: GitHub
• URL: https://github.com/rggen/rggen
• Owner: rggen
• License: mit
• Created: 2019-04-10T09:41:17.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2023-12-17T14:24:40.000Z (7 months ago)
• Last Synced: 2023-12-17T15:29:54.936Z (7 months ago)
• Topics: amba, apb, asic, axi, csr, eda, fpga, ral, register-descriptions, rtl, soc, systemverilog, uvm, uvm-ral-model, uvm-register-model, verilog, vhdl, wiki-documents, wishbone-bus
• Language: Ruby
• Homepage:
• Size: 497 KB
• Stars: 257
• Watchers: 14
• Forks: 36
• Open Issues: 12
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE
  • Code of conduct: CODE_OF_CONDUCT.md

Lists

• awesome-hdl - RgGen - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications (Other Design Automation tools)
• awesome-opensource-hardware - rggen
• awesome-opensource-asic-resources - RgGen - CSR generator (SystemVerilog/Verilog/VHDL RTL, UVM reg model etc) (Generators)
• awesome-hdl - RgGen - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications (Other Design Automation tools)
• awesome-stars - rggen/rggen - Code generation tool for control and status registers (Ruby)
• awesome-stars - rggen/rggen - Code generation tool for control and status registers (Ruby)

README

        
![RgGen](logo/rggen.png)

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# RgGen

RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.

RgGen has following features:

* Generate source files related to CSR from register map specifications

    * RTL module

        * SystemVerilog

        * Verilog

            * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin

        * VHDL

            * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin

        * Supports standard bus protocols

            * AMBA APB

            * AMBA AXI4-Lite

            * Wishbone

    * UVM register model (UVM RAL/uvm_reg)

    * C header file

    * Register map documents written in Markdown

* Register map specifications can be written in human readable format

    * Ruby with APIs to describe register map information

    * YAML

    * JSON

    * TOML

    * Spreadsheet (XLSX, ODS, CSV)

    * [SiFive DUH](https://github.com/sifive/duh)

        * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin

* Plugin feature

    * Allow you to customize RgGen for your environment

        * Add your own special bit field types

        * Add your own host bus protocol

## Installation

### Ruby

RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 3.0 or later. You need to install  any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/documentation/installation/).

### Installatin Command

RgGen depends on following sub components and other Ruby libraries.

* [rggen-core](https://github.com/rggen/rggen-core)

* [rggen-default-register-map](https://github.com/rggen/rggen-default-register-map)

* [rggen-systemverilog](https://github.com/rggen/rggen-systemverilog)

* [rggen-c-header](https://github.com/rggen/rggen-c-header)

* [rggen-markdown](https://github.com/rggen/rggen-markdown)

* [rggen-spreadsheet-loader](https://github.com/rggen/rggen-spreadsheet-loader)

To install RgGen and the dependencies, use the command below:

```

$ gem install rggen

```

RgGen and dependencies will be installed on your system root.

If you want to install them on other location, you need to specify install path and set `GEM_PATH` and `PATH` environment variables:

```

$ gem install --install-dir /path/to/your/install/directory rggen

$ export GEM_PATH=/path/to/your/install/directory

$ export PATH=$GEM_PATH/bin:$PATH

```

You would get the following error message duaring installation if you have the old RgGen (version < 0.9).

```

ERROR:  Error installing rggen:

        "rggen" from rggen-core conflicts with installed executable from rggen

```

To resolve the above error, there are three solutions.

See [this page](https://github.com/rggen/rggen/wiki/Resolve-Confliction-of-Installed-Executable)

### Docker Image

The [rggen-docker](https://hub.docker.com/r/rggendev/rggen-docker) is a Docker image to simplify installation and use of RgGen.

You can also execute RgGen by using this image:

```

$ docker run -ti --rm -v ${PWD}:/work --user $(id -u):$(id -g) rggendev/rggen-docker:latest -c config.yml -o out block_0.yml

```

See the [rggen-docker repository](https://github.com/rggen/rggen-docker) for further details.

## Usage

See [Wiki documents](https://github.com/rggen/rggen/wiki).

## Plugin

RgGen has `plugin` feature to allow your cusomization.

See [this Wiki document](https://github.com/rggen/rggen/wiki/Create-Your-Own-Plugin) for futher detals.

## Supported Tools

Following EDA tools can accept the generated source files.

* Simulation tools

    * Synopsys VCS

    * Cadence Xcelium

    * Xilinx Vivado Simulator

    * Verilator

        * Need `-Wno-unoptflat` switch for Verilog RTL

    * Icarus Verilog

        * Verilog RTL only

* Synthesis tools

    * Synopsys Design Compiler

    * Intel Quartus

    * Xilinx Vivado

    * [Yosys](http://www.clifford.at/yosys/)

        * Verilog RTL

## Example

You can get sample configuration file and register map specification from the [rggen-sample](https://github.com/rggen/rggen-sample) repository.

This register map specification is for a UART IP.

* Configuration file

    * https://github.com/rggen/rggen-sample/blob/master/config.yml

* Register map specification

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml

You can try to use RgGen by uisng these example files. Hit command below:

```

$ rggen -c config.yml -o out uart_csr.yml

```

* `-c`: Specify path to your configuration file

* `-o`: Specify path to the directory where generated files will be written to

Then, generated files will be written to the `out` directory.

If you want to generate Verilog RTL and/or VHDL RTL then you need to instll optional plugins listed below.

* Verilog writer plugin: [rggen-verilog](https://github.com/rggen/rggen-verilog)

* VHDL writer plugin: [rggen-vhdl](https://github.com/rggen/rggen-vhdl)

```

$ gem install rggen-verilog

$ gem install rggen-vhdl

```

In addition, you need to tell RgGen to use these plugins by using the `--plugin` option switch:

```

rggen -c config.yml --plugin rggen-verilog --plugin rggen-vhdl uart_csr.yml

```

RgGen will generate following source files from the [`uart_csr.yml`](https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml) register map specification:

* SystemVerilog RTL

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.sv

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr_rtl_pkg.sv

* Verilog RTL

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.v

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vh

* VHDL RTL

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vhd

* UVM register model

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr_ral_pkg.sv

* C header file

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.h

* Markdown document

    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.md

## Contributing

See [Contributing Guide](CONTRIBUTING.md).

## Contact

Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:

* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)

* [GitHub Discussions](https://github.com/rggen/rggen/discussions)

* [Chat Room](https://gitter.im/rggen/rggen)

* [Mailing List](https://groups.google.com/d/forum/rggen)

* [Mail](mailto:[email protected])

## See Also

* https://github.com/rggen/rggen-core

* https://github.com/rggen/rggen-default-register-map

* https://github.com/rggen/rggen-systemverilog

* https://github.com/rggen/rggen-c-header

* https://github.com/rggen/rggen-markdown

* https://github.com/rggen/rggen-spreadsheet-loader

* https://github.com/rggen/rggen-duh

* https://github.com/rggen/rggen-verilog

* https://github.com/rggen/rggen-vhdl

* https://github.com/rggen/rggen-docker

## Copyright & License

Copyright © 2019-2024 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.

## Code of Conduct

Everyone interacting in the RgGen project’s codebases, issue trackers, chat rooms and mailing lists is expected to follow the [code of conduct](CODE_OF_CONDUCT.md).