https://github.com/verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research
https://github.com/verilog-to-routing/vtr-verilog-to-routing

cad eda fpga placement routing synthesis verilog vpr vtr

Last synced: 3 months ago
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Verilog to Routing -- Open Source CAD Flow for FPGA Research

• Host: GitHub
• URL: https://github.com/verilog-to-routing/vtr-verilog-to-routing
• Owner: verilog-to-routing
• License: other
• Created: 2015-06-26T15:24:42.000Z (about 9 years ago)
• Default Branch: master
• Last Pushed: 2024-03-20T14:36:19.000Z (3 months ago)
• Last Synced: 2024-03-20T15:56:22.689Z (3 months ago)
• Topics: cad, eda, fpga, placement, routing, synthesis, verilog, vpr, vtr
• Language: C++
• Homepage: https://verilogtorouting.org
• Size: 290 MB
• Stars: 939
• Watchers: 68
• Forks: 368
• Open Issues: 450
• Metadata Files:
  • Readme: README.developers.md
  • Changelog: CHANGELOG.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE.md
  • Support: SUPPORT.md

Lists

• awesome-hdl - vtr-verilog-to-routing
• awesome-opensource-hardware - vtr
• awesome-hdl - vtr-verilog-to-routing
• awesome-stars - verilog-to-routing/vtr-verilog-to-routing - Verilog to Routing -- Open Source CAD Flow for FPGA Research (C++)
• awesome-stars - verilog-to-routing/vtr-verilog-to-routing - Verilog to Routing -- Open Source CAD Flow for FPGA Research (C++)
• awesome-eda - Verilog to Routing -- Open Source CAD Flow for FPGA Research