https://github.com/The-OpenROAD-Project/TritonCTS

Source codes and calibration scripts for clock tree synthesis
https://github.com/The-OpenROAD-Project/TritonCTS

Last synced: 3 months ago
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Source codes and calibration scripts for clock tree synthesis

• Host: GitHub
• URL: https://github.com/The-OpenROAD-Project/TritonCTS
• Owner: The-OpenROAD-Project
• License: bsd-3-clause
• Archived: true
• Created: 2018-09-12T14:47:10.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2020-02-18T16:34:20.000Z (over 4 years ago)
• Last Synced: 2024-03-21T16:07:44.804Z (3 months ago)
• Language: C++
• Homepage:
• Size: 112 MB
• Stars: 36
• Watchers: 6
• Forks: 11
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Lists

• awesome-eda - TritoCTS

README

        
# TritonCTS 

### ------------------------------- WARNING --------------------------------

### :bangbang: This version of TritonCTS has been retired from the OpenROAD flow. :bangbang: 

### :bangbang: You can find TritonCTS 2.0 [here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/TritonCTS). :bangbang:

### --------------------------------------------------------------------------

### Original work

K. Han, A. B. Kahng and J. Li, "Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution", IEEE Trans. on CAD (2018), [doi:10.1109/TCAD.2018.2889756](https://doi.org/10.1109/TCAD.2018.2889756).

Many subsequent changes for open-sourcing were made by [Mateus Fogaça](https://github.com/mpfogaca).

### Inputs and outputs

TritonCTS requires 5 input files and produces 2 output files. Refer to [OpenROAD Flow and Notes](https://theopenroadproject.org/wp-content/uploads/2018/12/OpenROAD_Flow_and_Notes_Nov2018-v1p0-1.pdf) for more information.

Inputs:

- [Library characterization files](doc/Technology_characterization.md)

- Verilog with gate-level netlist

- Placed DEF with netlist

- [Configuration file](doc/Run_TritonCTS.md#example-of-a-config-file)

Outputs:

- Placed DEF with clock buffers

- Verilog with clock buffers

### Supported features / assumptions

- 1 clock source;

### Validation

TritonCTS has been validated for the following list of platforms, tools and enablements.

| Feature | Support |

|---|---|

| Operating system | CentOS 6 |

| Compiler  | GCC 4.4.7 |

| Enablements | ST28 and TSMC16 |

| TCL | Version 8.4.20 |

| Python | Version 2.7.12 |

| [Lemon](https://lemon.cs.elte.hu/trac/lemon) | Version 1.3.1 |

### Tutorials

- [Run the library characterization](doc/Technology_characterization.md)

- [Compile and run TritonCTS](doc/Run_TritonCTS.md)

### Example

Below we display the clock nets for the design jpeg_encoder implemented in TSMC65 with 24K instances, followed by TritonCTS routing topology.

|  |

|:--:|

| *TritonCTS generated clock nets for jpeg_encoder* |

|  |

|:--:| 

| *TritonCTS clock tree topology for jpeg_encoder* |