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https://github.com/upscale-project/hslink_phy
Verilog functional model for PHY
https://github.com/upscale-project/hslink_phy
Last synced: 3 months ago
JSON representation
Verilog functional model for PHY
- Host: GitHub
- URL: https://github.com/upscale-project/hslink_phy
- Owner: upscale-project
- License: bsd-3-clause
- Created: 2019-01-10T23:44:29.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2019-06-27T00:36:16.000Z (about 5 years ago)
- Last Synced: 2024-01-18T13:08:43.957Z (5 months ago)
- Language: Python
- Size: 3.29 MB
- Stars: 7
- Watchers: 4
- Forks: 6
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Lists
- awesome-eda - Serial Link Mixed Signal Modeling
README
# Open Source PHY Architecture
## Introduction
This repository contains an ADC-based high-speed link design, along with the behavioral models and simulation framework needed to test it. Certain parts of the design are parameterized (such as the number of filter taps), and it's possible to simulate the link behavior for an arbitrary channel by providing a file of S-parameters.
## Running the demo
1. First set up the shell environment:
```shell
> source setup.cshrc
```
2. Then go into the channel/model folder:
```shell
> cd channel/model
```
3. Build the channel models:
```shell
> make
```
4. Next, go into the architect/sim folder:
```shell
> cd ../../architect/sim
```
5. Run the simulation:
```shell
> make
```
6. View the simulation waveforms with SimVision.
```shell
> simvision
```
