https://github.com/uwidea/UW-IDEA_AnalogTestCases

Circuit Release for Analog Test Cases from UW IDEA project
https://github.com/uwidea/UW-IDEA_AnalogTestCases

Last synced: 3 months ago
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Circuit Release for Analog Test Cases from UW IDEA project

• Host: GitHub
• URL: https://github.com/uwidea/UW-IDEA_AnalogTestCases
• Owner: uwidea
• License: apache-2.0
• Created: 2019-05-24T21:57:06.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2022-09-14T20:36:33.000Z (almost 2 years ago)
• Last Synced: 2024-01-18T13:08:46.802Z (5 months ago)
• Language: Verilog
• Homepage:
• Size: 10.3 MB
• Stars: 8
• Watchers: 1
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Lists

• awesome-eda - UW-IDEA_AnalogTestCases

README

        
# UW-IDEA_AnalogTestCases

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Circuit release for Analog Test Cases from UW IDEA project

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* All designs are fabricated and tested

* Contains hierarchical schematic, documentation, parameterized Hspice netlist and sanitized CDL netlist. 

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Circuits

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* The known good design (KGD) IPs that are illustrated in the following table can be found in the folder AMS_KGD 

| Circuit       | Architecture               | Design File Location          |

| :------------:| ------------------ | -------------------|

| SAR_ADC | 12b SAR ADC | AMS_KGD/SAR_ADC |

| DLDO | Digital LDO | AMS_KGD/DLDO |

| MDLL | Multiplying DLL  |	AMS_KGD/MDLL|

| TX | Transmitter | AMS_KGD/Transmitter |

| TS | Temperature Sensor  | AMS_KGD/TempSensor |

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Modules

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* The modules that build up the above circuits are included in the folder Module.

* The modules for the SAR ADC

* The modules for the transmitter

* The modules for the temperature sensor