https://github.com/pConst/basic_verilog

Must-have verilog systemverilog modules
https://github.com/pConst/basic_verilog

altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx

Last synced: 3 months ago
JSON representation

Must-have verilog systemverilog modules

• Host: GitHub
• URL: https://github.com/pConst/basic_verilog
• Owner: pConst
• Created: 2015-12-14T18:09:40.000Z (over 8 years ago)
• Default Branch: master
• Last Pushed: 2023-12-14T21:13:40.000Z (7 months ago)
• Last Synced: 2024-01-08T01:44:17.347Z (6 months ago)
• Topics: altera, debounce, delay, encoder, fifo, fpga, hls, pwm, spi-interface, spi-master, synchronizer, tcl, uart, uart-controller, uart-protocol, uart-receiver, uart-tx, uart-verilog, verilog, xilinx
• Language: Verilog
• Homepage:
• Size: 54.2 MB
• Stars: 1,348
• Watchers: 56
• Forks: 311
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: license/88x31.png

Lists

• awesome-opensource-hardware - basic_verilog
• awesome-stars - pConst/basic_verilog - Must-have verilog systemverilog modules (Verilog)
• awesome-opensource-hardware-repos - basic_verilog
• awesome-digital-ic - Must-have verilog systemverilog modules - A collection of verilog systemverilog synthesizable modules. (Projects and IPs / Quora Topics)
• ASIC-Design-Roadmap - Must-have verilog systemverilog modules - A collection of verilog systemverilog synthesizable modules. (Projects and IPs / Quora Topics)