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https://github.com/fukatani/awesome-hdl
A curated list of awesome HDL, libraries, typical implementation and references.
https://github.com/fukatani/awesome-hdl
List: awesome-hdl
Last synced: about 2 months ago
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A curated list of awesome HDL, libraries, typical implementation and references.
- Host: GitHub
- URL: https://github.com/fukatani/awesome-hdl
- Owner: fukatani
- License: cc0-1.0
- Created: 2016-09-24T00:57:39.000Z (almost 8 years ago)
- Default Branch: master
- Last Pushed: 2016-10-19T16:54:35.000Z (over 7 years ago)
- Last Synced: 2024-02-05T09:52:23.207Z (5 months ago)
- Homepage:
- Size: 5.86 KB
- Stars: 30
- Watchers: 3
- Forks: 3
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
Lists
- awesome - fukatani/awesome-hdl
- awesome-cuda-tensorrt-fpga - fukatani/awesome-hdl - hdl?style=social"/> : A curated list of awesome HDL, libraries, typical implementation and references. (Awesome List)
README
# Awesome HDL [](https://github.com/sindresorhus/awesome)
A curated list of awesome HDL, libraries and implementation (by language). Inspired by awesome-machine-learning.
If you want to contribute to this list (please do), please feel free to send me a pull request .
## Table of Contents
- [Verilog-Toolkit](#verilog-toolkit)
- [Verilog-Implementation](#verilog-implementation)
- [Verilog-Books](#verilog-books)
- [VHDL-Toolkit](#vhdl-toolkit)
- [VHDL-Implementation](#vhdl-implementation)
- [Tutorial](#tutorial)
- [Paper](#paper)
## Verilog-Toolkit
* [Icarus Verilog](https://github.com/steveicarus/iverilog) - A Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
* [verilog-mode](https://github.com/veripool/verilog-mode) - Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs.
* [Pyverilog](https://github.com/PyHDI/Pyverilog) - Python-based Hardware Design Processing Toolkit for Verilog HDL.
* [veriloggen](https://github.com/PyHDI/veriloggen) - A library for constructing a Verilog HDL source code by Python.
* [PyCoRAM](https://github.com/PyHDI/PyCoRAM) - Python-based Portable IP-core Synthesis Framework for FPGA-based Computing.
* [Pyverilog-toolbox](https://github.com/fukatani/Pyverilog_toolbox) - Pyverilog-based verification/design tool including code clone finder, metrics calculator and so on.
## Hardware-Implementation-by-Verilog
* [miaow](https://github.com/VerticalResearchGroup/miaow) - An open source GPU based off of the AMD Southern Islands ISA.
* [amiga2000-gfxcard](https://github.com/mntmn/amiga2000-gfxcard) - MNT VA2000, an Amiga 2000 Graphics Card (Zorro II), written in Verilog.
* [gplgpu](https://github.com/asicguy/gplgpu) - GPL v3 2D/3D graphics engine in verilog.
* [oh](https://github.com/parallella/oh) - Silicon validated Open Verilog library for IC and FPGA designers.
* [FPGA-Litecoin-Miner](https://github.com/kramble/FPGA-Litecoin-Miner) - Litecoin script miner implemented with FPGA on-chip memory.
* [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) - Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths).
## Verilog-Books
* [SystemVerilog Assertions Handbook](https://verificationacademy.com/forums/systemverilog/new-book-systemverilog-assertions-handbook-4th-edition) - Assertion Guide for static and dynamic verification.
* [Writing Testbenches using SystemVerilog](http://www.springer.com/us/book/9780387292212) - Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source.
## VHDL-Toolkit
* [sublime-vhdl](https://github.com/yangsu/sublime-vhdl) - VHDL Package for Sublime Text 2/3.
* [nvc](https://github.com/nickg/nvc) - VHDL compiler and simulator.
* [vunit](https://github.com/VUnit/vunit) - A unit testing framework for VHDL/SystemVerilog.
## Hardware-Implementation-by-VHDL
* [Open-Source-FPGA-Bitcoin-Miner](https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner) - A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs.
* [space-invaders-vhdl](https://github.com/fabioperez/space-invaders-vhdl) - Space Invaders game implemented with VHDL.
* [IntroToSpartanFPGABook](https://github.com/hamsternz/IntroToSpartanFPGABook) - A book on using the Spartan 3E FPGA with VHDL, using the Papilio One or Digilent Basys2 boards.
* [EDA playground](https://www.edaplayground.com/) - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
* [Asynchronous & Synchronous Reset Design Techniques](http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf)
* [Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog](http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf)