https://github.com/64/rave32

An unpipelined 32-bit RISC-V CPU, written in Chisel.
https://github.com/64/rave32

chisel hardware risc-v rtl

Last synced: 12 months ago
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An unpipelined 32-bit RISC-V CPU, written in Chisel.

• Host: GitHub
• URL: https://github.com/64/rave32
• Owner: 64
• License: mit
• Created: 2022-12-20T22:22:07.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2022-12-29T23:05:16.000Z (about 3 years ago)
• Last Synced: 2025-01-13T02:46:00.944Z (about 1 year ago)
• Topics: chisel, hardware, risc-v, rtl
• Language: Scala
• Homepage:
• Size: 56.6 KB
• Stars: 1
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.md

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README

          
Rave32: A RV32E CPU

=======================

This is an unpipelined RV32E (RISC-V 32-bit, embedded variant) CPU written in Chisel.

Tests can be run with `sbt test`.