https://github.com/DFiantHDL/DFHDL

DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
https://github.com/DFiantHDL/DFHDL

asic dataflow dataflow-programming fpga hdl

Last synced: 3 months ago
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DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

• Host: GitHub
• URL: https://github.com/DFiantHDL/DFHDL
• Owner: DFiantHDL
• License: lgpl-3.0
• Created: 2019-06-16T19:42:03.000Z (over 5 years ago)
• Default Branch: main
• Last Pushed: 2024-08-03T03:40:24.000Z (3 months ago)
• Last Synced: 2024-08-03T09:22:08.869Z (3 months ago)
• Topics: asic, dataflow, dataflow-programming, fpga, hdl
• Language: Scala
• Homepage: https://dfianthdl.github.io/
• Size: 49.4 MB
• Stars: 75
• Watchers: 7
• Forks: 8
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: COPYING.LESSER

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• awesome-opensource-hardware - dfiant

README

        
# DFiant HDL

---

![Build Status](https://github.com/DFiantHDL/DFiant/workflows/Build/badge.svg)

[![dfhdl Scala version support](https://index.scala-lang.org/dfianthdl/dfhdl/dfhdl/latest.svg)](https://index.scala-lang.org/dfianthdl/dfhdl/dfhdl)

[![Discord Chat](https://img.shields.io/discord/721461308297576598.svg)](https://discord.gg/) 

[![Scala Steward badge](https://img.shields.io/badge/Scala_Steward-helping-blue.svg?style=flat&logo=data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAA4AAAAQCAMAAAARSr4IAAAAVFBMVEUAAACHjojlOy5NWlrKzcYRKjGFjIbp293YycuLa3pYY2LSqql4f3pCUFTgSjNodYRmcXUsPD/NTTbjRS+2jomhgnzNc223cGvZS0HaSD0XLjbaSjElhIr+AAAAAXRSTlMAQObYZgAAAHlJREFUCNdNyosOwyAIhWHAQS1Vt7a77/3fcxxdmv0xwmckutAR1nkm4ggbyEcg/wWmlGLDAA3oL50xi6fk5ffZ3E2E3QfZDCcCN2YtbEWZt+Drc6u6rlqv7Uk0LdKqqr5rk2UCRXOk0vmQKGfc94nOJyQjouF9H/wCc9gECEYfONoAAAAASUVORK5CYII=)](https://scala-steward.org)

Welcome to the DFiant hardware description language (DFHDL) repository! 

DFHDL is a dataflow HDL and is embedded as a library in the [Scala programming language](https://www.scala-lang.org/). DFiant enables timing-agnostic and device-agnostic hardware description by using dataflow firing rules as logical constructs, coupled with modern software language features (e.g., inheritance, polymorphism, pattern matching) and classic HDL features (e.g., bit-accuracy, input/output ports). Additionally, DFHDL integrates two additional levels of hardware description abstractions: register-transfer (RT), which is equivalent to languages like Chisel and Amaranth; and event-driven (ED), which is equivalent to Verilog and VHDL. 

Read the documentation: https://dfianthdl.github.io/

## Acknowledgement

Previous version of this work (simply called "DFiant" at the time) has been supported by EU H2020 ICT project LEGaTO, contract #780681.