https://github.com/Elphel/eddr3

mirror of https://git.elphel.com/Elphel/eddr3
https://github.com/Elphel/eddr3

ddr ddr3 fpga memory-controller open-core verilog xilinx zynq

Last synced: 23 days ago
JSON representation

mirror of https://git.elphel.com/Elphel/eddr3

• Host: GitHub
• URL: https://github.com/Elphel/eddr3
• Owner: Elphel
• Created: 2014-04-29T15:57:22.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2017-10-16T20:33:45.000Z (about 7 years ago)
• Last Synced: 2024-08-10T14:22:33.862Z (4 months ago)
• Topics: ddr, ddr3, fpga, memory-controller, open-core, verilog, xilinx, zynq
• Language: Verilog
• Homepage:
• Size: 1.49 MB
• Stars: 40
• Watchers: 12
• Forks: 17
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

        
eddr3

=====

ddr3 subproject for Elphel 393 camera

This subproject is started to create a DDR3 memory controller for Elphel camera that does not depend on any non-documented

features of Xilinx Zynq and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted

modules. Everything in plain Verilog and constraints.

Detailed description of the project is available in the blog post: http://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/