https://github.com/Featherweight-IP/fwrisc

Featherweight RISC-V implementation
https://github.com/Featherweight-IP/fwrisc

risc-v verilog zephyr

Last synced: 13 days ago
JSON representation

Featherweight RISC-V implementation

• Host: GitHub
• URL: https://github.com/Featherweight-IP/fwrisc
• Owner: Featherweight-IP
• License: apache-2.0
• Created: 2018-10-30T05:13:10.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2022-01-17T17:23:23.000Z (almost 3 years ago)
• Last Synced: 2024-08-01T01:27:49.987Z (3 months ago)
• Topics: risc-v, verilog, zephyr
• Language: SystemVerilog
• Size: 2.95 MB
• Stars: 52
• Watchers: 6
• Forks: 9
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • Changelog: ChangeLog.txt
  • License: LICENSE

Awesome Lists containing this project

• awesome-riscv - FWRISC-S - IP/fwrisc?label=★) (Open Source Core Implementations)

README

        
# FWRISC

[![Build Status](https://dev.azure.com/mballance/mballance/_apis/build/status/mballance.fwrisc?branchName=master)](https://dev.azure.com/mballance/mballance/_build/latest?definitionId=8&branchName=master)

FWRISC-S is a _Featherweight RISC-V_ implementation of the RV32IMC instruction set with

IoT-appropriate security features. This implementation supports the integer instructions,

registers, CSRs, and exceptions as required by the RISC-V spec.

This revision of the core was created for the 2019 RISC-V security contest:

https://riscv.org/2019/07/risc-v-softcpu-core-contest/

FWRISC is a non-pipelined processor that aims to balance performance with FPGA resource utilization. 

It achieves 0.15 DMIPS/Mhz.

FWRISC correctly runs all RISCV RV32I [compliance tests](https://github.com/riscv/riscv-compliance).

It also supports the [Zephyr](https://www.zephyrproject.org/) RTOS.

## Core Features

- RV32IMC instructions

- Multi-cycle shift

- Multi-cycle multiply/divide

- Support for the compressed-instruction ISA

- MINSTR, MCYCLE counters

- ECALL/EBREAK/ERET instrutions

- Support for address-alignment exceptions

## SEcurity Features

FWRISC-S implements Data Execution Prevention, as a way to prevent arbitrary code

execution. While more-complex protection techniques are appropriate for more-complex

systems, IoT systems typically run a fixed program that can be easily protected in

this way. 

The Zephyr SoC-support configuration has been setup such that data execution prevention

is configured just after kernel boot. Using linker symbols, the configuration

programs CSRs to only allow execution in the text section of the image. See 

[Zephyr](doc/fwrisc_zephyr.md) for more information.

## Resource Stats

The bare FWRISC-S 1.0.0 core consumes the following resources:

TargetLUTs/LCsRAMFrequency

Microsemi IGLOO2 (Synplify)2592 LUTs2x 64x1836.6Mhz

## Getting Started

See the [Quickstart](doc/fwrisc_quickstart.md) document to get started with FWRISC. For more 

detailed information, see the documents below.

- [Tools](doc/fwrisc_tools.md)

- [Setup](doc/fwrisc_setup.md)

- [Verification Environment](doc/fwrisc_verification.md)

- [Design Documents](doc/fwrisc_design.md)

- [Zephyr Port](doc/fwrisc_zephyr.md)