https://github.com/IntelLabs/riscv-vector

Vector Acceleration IP core for RISC-V*
https://github.com/IntelLabs/riscv-vector

Last synced: 2 months ago
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Vector Acceleration IP core for RISC-V*

• Host: GitHub
• URL: https://github.com/IntelLabs/riscv-vector
• Owner: IntelLabs
• License: mulanpsl-2.0
• Created: 2022-11-02T02:40:06.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2024-10-28T09:41:15.000Z (3 months ago)
• Last Synced: 2024-10-29T10:39:10.702Z (3 months ago)
• Language: Scala
• Size: 20 MB
• Stars: 144
• Watchers: 5
• Forks: 22
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: License.MulanPSL2
  • Security: security.md

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README

        
# riscv-vector

Vector Acceleration IP core for RISC-V*.  

## Introduction

Vector Acceleration IP core for RISC-V* is a flexible RISC-V Vector unit that aims to support RISC-V Vector extension. The interface is based on OVI (Open Vector Interface) in order to integrate with different scalar cores. The code is written with Chisel. 

## Status

So far, the arithmetic functional units are sufficiently tested. Other functions such as load/store and control flow only passed basic test.

> Arithmetic FUs are located at *src/main/scala/darecreek/exu/vfucore/*, which contains 64-bit FU cores (mask and permutation are VLEN-bit). You can write a wrapper to compose multiple 64-bit FUs into one VLEN-bit FU. In this project, the *exu/lanevfu* and *exu/crosslane* are FU wrappers (with VLEN=256).

**Note**: this project is suspended now.

## Architecture

As shown below, it is an out-of-order vector core with OVI interface (orange arrows). There are one arithmetic issue queue and one load/store issue queue, which can operate simultaneously. Each issue queue issues micro-ops in order, but it can be modified to out-of-order issuing potentially. 







Please refer to [Design Introduction](./doc/design.md) for more details.

## License

Only the OVI(Open Vector Interface) is under Solderpad Hardware License v2.1 and others follow the Mulan PSL v2.