https://github.com/Isotel/mixedsim

Hardware Design Tool - Mixed Signal Simulation with Verilog
https://github.com/Isotel/mixedsim

Last synced: 28 days ago
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Hardware Design Tool - Mixed Signal Simulation with Verilog

• Host: GitHub
• URL: https://github.com/Isotel/mixedsim
• Owner: Isotel
• Created: 2017-03-21T12:20:27.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2019-05-20T09:30:27.000Z (over 5 years ago)
• Last Synced: 2024-08-03T05:04:24.808Z (4 months ago)
• Language: Python
• Size: 304 KB
• Stars: 70
• Watchers: 13
• Forks: 7
• Open Issues: 1
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

• awesome-hwd-tools - Isotel/mixedsim - A mixed signal simulation approach using ngspice and yosys providing a library mapping to spice (Full Custom Design / Mixed Signal Design)

README

        
# Hardware Design Tool - Mixed Signal & Domain Simulation

Designing embedded applications typically involves analog, digital worlds, and embedded code. 

To be able to verify the concepts we strive for simulation tools that could verify all the 

worlds together, not only as a mixed-signal simulation but also to be able to include Verilog 

VHDL, as well as Embedded C code.

More info about the project: http://www.isotel.eu/mixedsim

## Content

- Eagle to Spice: Simulate existing (real) schematics instead of redrawing parts of it

- Yosys Verilog synthesis library for ngspice, and ltspice

- Mechatronis Example and visualization using Blender

- NgSpice Simulator as a Development Framework for Algorithm & Embedded Firmware Developers

## Motivation: Standard ngSpice Model Library

Motivation has started to collect, modify, repair and verify freely available spice models

into a common library.

Got interested to join, just open a case on github or [contact me directly](mailto:[email protected])