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https://github.com/Isotel/mixedsim
Hardware Design Tool - Mixed Signal Simulation with Verilog
https://github.com/Isotel/mixedsim
Last synced: about 2 months ago
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Hardware Design Tool - Mixed Signal Simulation with Verilog
- Host: GitHub
- URL: https://github.com/Isotel/mixedsim
- Owner: Isotel
- Created: 2017-03-21T12:20:27.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2019-05-20T09:30:27.000Z (over 5 years ago)
- Last Synced: 2024-04-26T06:35:19.813Z (5 months ago)
- Language: Python
- Size: 304 KB
- Stars: 69
- Watchers: 13
- Forks: 7
- Open Issues: 1
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