Full Custom Design

Layout Generation/ Manipulation

• ucb-art/BAG_framework - Berkeley Analog Generator
• VLSIDA/OpenRAM - open-source SRAM Compiler
• KLayout/klayout - scriptable Layout Viewer and Editor

Mixed Signal Design

• Isotel/mixedsim - A mixed signal simulation approach using ngspice and yosys providing a library mapping to spice

Simulation

• FabriceSalvaire/pyspice - Simulating and creating Spice Circuits with Python
• ngspice - Spice Simulator

Verification

• unihd-cag/skillbridge - A seamless python to Cadence Virtuoso Skill interface
• electronics-and-drives/SPAM - SPAM is a package management system for Cadence SKILL
• electronics-and-drives/ml2tikz - Virtuoso layout to tikzpicture
• MatthewLoveQUB/SKILL_Tools - Skill++ Tools including a test framework
• EDDRSoftware/oaFileParser - oaFile Parser
• scikit-rf/scikit-rf - RF and Microwave Design in scikit
• mph-/lcapy - Lcapy is a Python package for linear circuit analysis. It uses SymPy for symbolic mathematics.
• YosysHQ/PADRING - A padring generator for asics
• DegateCommunity/Degate - Tool for VLSI reverse engineering
• cap1tan/wafermap - A python package to plot maps of semiconductor wafers
• heitzmann/gdsstk - Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.
• tub-msc/ordec - Custom IC Design Platform

Open Source PDK

Verification

• leviathanch/libresiliconprocess - A 1um open process specification
• google/skywater-pdk - Open Source Process SkyWater 130nm

Semi Custom Design/ FPGAs

Hardware Description Languages

• phanrahan/Magma - A Hardware Description Language embedded in Python
• llvm/circt - Intermediate representation for rtl (used by Chisel)
• myhdl/MyHDL - Python as a Hardware Description and Verification Language
• clash-lang/clash-compiler - A Hardware Description Language written and inspired by Haskell
• drom/awesome-hdl

Modelling

• mortbopet/VSRTL - Visual Simulation of Register Transfer Logic

Simulation

• steveicarus/iverilog - Icarus Verilog Simulator
• ghdl/ghdl - VHDL Simulator

Synthesis

• YosysHQ/yosys - Synthesis Flow

Timing Analysis

• OpenTimer/OpenTimer - timing analysis tool for vlsi systems

Verification

• cocotb/cocotb - Creating Verilog/VHDL testbenches with python

Wave Viewers

• wavedrom/wavedrom - Timing Diagrams in Java Script
• gtkwave - GTK based waveform viewer

• Nic30/hdlConverter - Python System-Verilog/VHDL Parser
• christiklein/simpy - discrite event based simulation framework
• chipmuenk/pyFDA - A python tool to design time discrete filters
• efabless/openlane - Automated RTL to GDS flow based on openRoad, Yosys and more...
• ahmed-agiza/EDAViewer - EDAV is a cloud-based open-source viewer for electronic design automation (EDA) design files (LEF, DEF)
• verilator/rtlmeter - RTLMeter benchmark suite