https://github.com/leviathanch/libresiliconprocess

https://github.com/leviathanch/libresiliconprocess

Last synced: 26 days ago
JSON representation

• Host: GitHub
• URL: https://github.com/leviathanch/libresiliconprocess
• Owner: leviathanch
• Created: 2017-12-14T17:27:55.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2019-08-19T23:33:48.000Z (over 5 years ago)
• Last Synced: 2024-08-04T20:02:31.375Z (4 months ago)
• Language: TeX
• Size: 139 MB
• Stars: 30
• Watchers: 11
• Forks: 13
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

• awesome-hwd-tools - leviathanch/libresiliconprocess - A 1um open process specification (Open Source PDK / Verification)

README

        
# Libre Silicon v0.1

This is the LibreSilicon process specification (WIP)

Please use XeLaTeX for rendering the documents

Features are:

* 1 micron (1 um)

* twin-well for cmos

* pbase / nbase (optional) for bipolar

* shallow trench isolation

* sonos for flash (optional)

* silicification

aiming higher voltages, higher speed and higher feasibilty for modern Analog and System-on-Chip design.