https://github.com/mortbopet/VSRTL

Visual Simulation of Register Transfer Logic
https://github.com/mortbopet/VSRTL

Last synced: about 1 month ago
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Visual Simulation of Register Transfer Logic

• Host: GitHub
• URL: https://github.com/mortbopet/VSRTL
• Owner: mortbopet
• License: mit
• Created: 2019-01-28T14:56:23.000Z (almost 6 years ago)
• Default Branch: master
• Last Pushed: 2023-11-04T14:02:00.000Z (about 1 year ago)
• Last Synced: 2024-05-18T20:24:59.542Z (7 months ago)
• Language: C++
• Size: 15.9 MB
• Stars: 84
• Watchers: 7
• Forks: 16
• Open Issues: 29
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-hwd-tools - mortbopet/VSRTL - Visual Simulation of Register Transfer Logic (Semi Custom Design/ FPGAs / Modelling)

README

        
# VSRTL

[![VSRTL build and test](https://github.com/mortbopet/VSRTL/actions/workflows/build-and-test.yml/badge.svg?branch=master)](https://github.com/mortbopet/VSRTL/actions/workflows/build-and-test.yml)

[![Gitter](https://badges.gitter.im/Ripes-VSRTL/VSRTL.svg)](https://gitter.im/Ripes-VSRTL/)

***V**isual **S**imulation of **R**egister **T**ransfer **L**ogic*

VSRTL is a framework for describing, visualizing and simulating digital circuits.  

A VSRTL-described circuit may be built and simulated as a standalone application or embedded within a Qt-based C++ application. As an example, VSRTL is used as the simulation and visualization framework for [Ripes](https://github.com/mortbopet/Ripes), a graphical processor simulator and assembly editor for the RISC-V ISA.

Refer to the [reference section](docs/README.md) for implementation and usage documentation.  

If you would like to contribute, check the [issues](https://github.com/mortbopet/vsrtl/issues) section - There's plenty of work to be done!  

For questions, comments, feature requests, or new ideas, don't hesitate to share these at [the discussions page](https://github.com/mortbopet/VSRTL/discussions).



  



Figure: A visualization of [VelonaCore](https://github.com/mortbopet/VelonaCore), a single cycle processor implementing the [Leros instruction set](https://leros-dev.github.io).

# Building

```

git clone --recurse-submodules https://github.com/mortbopet/VSRTL.git

cd VSRTL/

cmake .

make -j$(nproc)

```

## Dependencies:

* **Core**

  * C++17 toolchain

  * CMake

* **Graphics**

  * Qt 6.5.0+: https://www.qt.io/download

---

In papers and reports, please refer to VSRTL as follows: 'Morten Borup Petersen. VSRTL. https://github.com/mortbopet/VSRTL', e.g. using the following BibTeX code:

```

@MISC{VSRTL,

	author = {Morten Borup Petersen},

	title = {VSRTL: Visual Simulation of Register Transfer Logic},

	howpublished = "\url{https://github.com/mortbopet/VSRTL}"

}

```