https://github.com/PrincetonUniversity/prga

Open-source FPGA research and prototyping framework.
https://github.com/PrincetonUniversity/prga

Last synced: 3 months ago
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Open-source FPGA research and prototyping framework.

• Host: GitHub
• URL: https://github.com/PrincetonUniversity/prga
• Owner: PrincetonUniversity
• License: bsd-3-clause
• Created: 2019-01-03T20:31:30.000Z (about 6 years ago)
• Default Branch: release
• Last Pushed: 2023-01-12T15:47:42.000Z (almost 2 years ago)
• Last Synced: 2024-07-31T19:17:28.470Z (5 months ago)
• Language: SCSS
• Homepage: http://parallel.princeton.edu/prga/
• Size: 1.62 MB
• Stars: 193
• Watchers: 15
• Forks: 24
• Open Issues: 5
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-opensource-hardware - prga

README

        
[![PRGA logo](/docs/source/_static/images/logo.png)](https://parallel.princeton.edu/prga)

# **P**rinceton **R**econfigurable **G**ate **A**rray

[![License](https://img.shields.io/badge/License-BSD%203--Clause-blue.svg)](https://opensource.org/licenses/BSD-3-Clause)

[![Documentation Status](https://readthedocs.org/projects/prga/badge/?version=latest)](https://prga.readthedocs.io/en/latest/?badge=latest)

[![ci-install](https://github.com/PrincetonUniversity/prga/actions/workflows/checkinstall.yml/badge.svg?branch=release)](https://github.com/PrincetonUniversity/prga/actions/workflows/checkinstall.yml)

[![ci-dev](https://github.com/PrincetonUniversity/prga/actions/workflows/quickcheck.yml/badge.svg?branch=dev)](https://github.com/PrincetonUniversity/prga/actions/workflows/quickcheck.yml)

Build your own FPGA Chip or embedded FPGA IP with Python, and enjoy a fully

open-source, auto-generated CAD flow specifically for your custom FPGA.

#### Find out more

* [Documentation](https://prga.rtfd.io)

* [Website](https://parallel.princeton.edu/prga/)

* [Cite PRGA](https://dl.acm.org/doi/abs/10.1145/3431920.3439294)

## Quickstart

```bash

# Install PRGA and dependencies

cd /path/to/prga/

./envscr/install

# Install iverilog (Icarus Verilog) if Synopsys VCS is not available

# ...

# Activate Python virtual environment

source ./envscr/activate

# build an example FPGA

make -C examples/fpga/magic/k4_N2_8x8

# create CAD & verification project

make -C examples/app/bcd2bin/magic_k4_N2_8x8

# run RTL-to-bitstream flow and post-implementation simulation

make -C examples/app/bcd2bin/magic_k4_N2_8x8/tests/basic

```