https://github.com/Redcrafter/verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
https://github.com/Redcrafter/verilog2factorio
compiler factorio verilog
Last synced: 6 months ago
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This project will compile verilog (a hardware description language) into factorio blueprints.
- Host: GitHub
- URL: https://github.com/Redcrafter/verilog2factorio
- Owner: Redcrafter
- License: gpl-3.0
- Created: 2021-03-21T14:14:04.000Z (over 4 years ago)
- Default Branch: main
- Last Pushed: 2025-02-03T01:26:35.000Z (10 months ago)
- Last Synced: 2025-02-03T02:25:28.829Z (10 months ago)
- Topics: compiler, factorio, verilog
- Language: TypeScript
- Homepage: https://redcrafter.github.io/verilog2factorio/
- Size: 6.65 MB
- Stars: 768
- Watchers: 8
- Forks: 21
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Factorio verilog compiler
This project will compile verilog (a hardware description language) into factorio blueprints.\
Using [this](https://github.com/ghdl/ghdl-yosys-plugin) it should also be possible to compile vhdl. (not tested)
## Web Demo
You can check out the web demo [here](https://redcrafter.github.io/verilog2factorio).
## Install
Manually compile [Yosys 0.34](https://github.com/YosysHQ/yosys/releases/tag/yosys-0.34) (later releases might not work) and add it to your PATH.
Run ``` npm install ``` to install all dependencies.
## Usage
```
Usage: v2f [options]
Options:
-v, --verbose
-d --debug Generate debug information. (A graph of the output circuit.)
-o, --output File to output the compiled blueprint to.
-m, --modules Verilog modules to output blueprint for. (defaults to all).
-f, --files List of Verilog files to compile. (only has to be explicitly specified after -m).
-g, --generator [type] Layout generator to use. annealing(default),matrix,chunkAnnealing
-h, --help Display this information.
```
## Quick Start
Run ```./v2f``` with verilog files as parameters. Example: `./v2f ./samples/counter.v`
The compiled blueprint will be output on the command line unless otherwise specified with `-f`.
The circuit will have inputs and outputs at the top in the order in which they were written in the code.
Clock pulses are required to be exactly one tick high. (since adding edge detectors would produce a lot of overhead)
## Examples
### samples/counter.v
```verilog
module counter(input clk, input rst, input inc, output reg [3:0] cnt);
always @(posedge clk) begin
if (rst)
cnt <= 0;
else if (inc)
cnt <= cnt + 1'b1;
end
endmodule
```
At the top in order clk, rst, inc and cnt.
### 6502 CPU from https://github.com/Arlet/verilog-6502/
using the new layout method "chunkAnnealing"
