https://github.com/Ronsor/riscv-zig

A RISC-V emulator written in Zig
https://github.com/Ronsor/riscv-zig

Last synced: about 1 month ago
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A RISC-V emulator written in Zig

• Host: GitHub
• URL: https://github.com/Ronsor/riscv-zig
• Owner: Ronsor
• License: mit
• Created: 2021-03-09T03:15:18.000Z (almost 4 years ago)
• Default Branch: master
• Last Pushed: 2021-06-12T01:15:00.000Z (over 3 years ago)
• Last Synced: 2024-08-02T22:27:35.464Z (4 months ago)
• Language: Zig
• Size: 10.7 KB
• Stars: 46
• Watchers: 3
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# RV64IM emulator

This repository contains a library for emulating RISC-V 64 CPUs with the multiply extension.

*Caveat emptor:* The implementation of RISC-V contained herein has not been tested for compliance.

It may produce incorrect results, and it most certainly does not reject all invalid instructions.

(C) 2021 Ronsor Labs.

## TODO

* Support RV32 too (should be easy)

* Implemented privileged instructions

* Better documentation