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https://github.com/THU-DSP-LAB/ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
https://github.com/THU-DSP-LAB/ventus-gpgpu

Last synced: 3 months ago
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GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Host: GitHub
URL: https://github.com/THU-DSP-LAB/ventus-gpgpu
Owner: THU-DSP-LAB
License: mulanpsl-2.0
Created: 2022-08-08T07:34:22.000Z (over 2 years ago)
Default Branch: master
Last Pushed: 2024-10-27T13:41:03.000Z (3 months ago)
Last Synced: 2024-10-27T18:42:43.810Z (3 months ago)
Language: Scala
Size: 30.9 MB
Stars: 614
Watchers: 14
Forks: 70
Open Issues: 3
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- License: LICENSE
- Codeowners: .github/CODEOWNERS

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README

# Ventus(乘影) GPGPU
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL.

We are calling for contributors. If you are interested in Ventus GPGPU, please contact [email protected]

“乘影”在RVV编译器工具链、验证环境开发和硬件设计方面还有很多不足，如果您有意愿参与到“乘影”的开发中，欢迎在github上pull request，也欢迎联系 [email protected]

乘影2.0架构文档在[这里](https://github.com/THU-DSP-LAB/ventus-gpgpu/blob/master/docs/乘影GPGPU架构文档手册v2.0.pdf)，添加了对OpenCL支持所需的改动。如果您在软硬件方面有任何建议，欢迎提issue或邮件联系。

乘影开源GPGPU项目网站：[opengpgpu.org.cn](https://opengpgpu.org.cn/)

Home page of Ventus-GPGPU project: [opengpgpu.org.cn](https://opengpgpu.org.cn/)

乘影软件工具链release版本在[这里](https://opengpgpu.org.cn/html/web/project/release/index.html)获取.

You can get the release version of software toolchain [here](https://opengpgpu.org.cn/html/web/project/release/index.html).

## Architecture

The micro-architecture overview of Ventus(乘影) is shown below.

ISA and micro-architecture docs is [here](https://github.com/THU-DSP-LAB/ventus-gpgpu/blob/master/docs/ventus%20GPGPU%20architecture%20whitepaper%20v2.0.pdf). Chinese docs is [here](https://github.com/THU-DSP-LAB/ventus-gpgpu/blob/master/docs/乘影GPGPU架构文档手册v2.0.pdf).

OpenCL C compiler based on LLVM is developed by Terapines([兆松科技](https://www.terapines.com/)).

Use the script in [ventus-llvm](https://github.com/THU-DSP-LAB/llvm-project) to configure the complete software toolchain, including [isa-simulator](https://github.com/THU-DSP-LAB/ventus-gpgpu-isa-simulator), [pocl](https://github.com/THU-DSP-LAB/pocl) and [driver](https://github.com/THU-DSP-LAB/pocl).

![](./docs/images/ventus_arch.png)

## Quick Start
[从零开始的配置教程](https://zhuanlan.zhihu.com/p/586445036)（中文，从WSL和IDEA安装讲起）

The tutorial of Chisel development environment configuration comes from [chipsalliance/playground: chipyard in mill :P](https://github.com/chipsalliance/playground)

0. Install dependencies and setup environments:
- Arch Linux
`pacman -Syu --noconfirm make parallel wget cmake ninja mill dtc verilator git llvm clang lld protobuf antlr4 numactl`
- Nix
`nix-shell`
- Ubuntu
```shell
apt-get install make parallel wget cmake verilator git llvm clang lld protobuf-compiler antlr4 numactl
curl -L https://github.com/com-lihaoyi/mill/releases/download/0.10.8/0.10.8 > mill && chmod +x mill
```
> We recomment using java 17 or higher versions.

1. Init and update dependences

```shell
make init
make patch
```

2. IDE support `make bsp # generate IDE bsp`

3. to generate verilog file, use `make verilog`. The output file is `GPGPU_top.v` . Notice that if you install 'mill' with 'curl', use `./mill ` to replace `mill` in Makefile commands.

4. to run tests, use `make tests`. Output waveform file is at `test_run_dir`

> Notice that current codes are not stable and there are conflicts between existing codes and testcase `gaussian` `gemm`. We are preparing new testcase format to integrate with software toolchain and please wait for our new version.

## Acknowledgement

We refer to some open-source design when developing Ventus GPGPU.

| Sub module | Source | Detail |
|---------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------|
| CTA scheduler | [MIAOW](https://github.com/VerticalResearchGroup/miaow) | Our CTA scheduler module is based on MiaoW ultra-threads dispatcher. |
| L2Cache | [block-inclusivecache-sifive](https://github.com/sifive/block-inclusivecache-sifive) | Our L2Cache design is inspired by Sifive's block-inclusivecache |
| Multiplier | [XiangShan](https://github.com/OpenXiangShan/XiangShan) | We reused Array Multiplier in XiangShan. FPU design is also inspired by XiangShan. |
| Config, ... | [rocket-chip](https://github.com/chipsalliance/rocket-chip) | Some modules are sourced from RocketChip |