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https://github.com/Thinklab-SJTU/awesome-ai4eda

Awesome Artificial Intelligence for Electronic Design Automation Papers.
https://github.com/Thinklab-SJTU/awesome-ai4eda

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Awesome Artificial Intelligence for Electronic Design Automation Papers.

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# Awesome Artificial Intelligence for Electronic Design Automation



We would like to maintain a list of resources that utilize artificial intelligence to solve Electronic Design Automation (EDA) problems.



We mark work contributed by [Thinklab](http://thinklab.sjtu.edu.cn) with ✨.



Also see our maintaining list for [LLM4EDA: Emerging Advancement in Large Language Models for Electronic Design Automation](https://github.com/Thinklab-SJTU/Awesome-LLM4EDA).



*Maintained by members in SJTU-Thinklab: Xingbo Du, Ruoyu Cheng, Ruizhe Zhong, Peiyu Wang, Jianyong Yuan, Chonghua Wang* 



## [Content](#content)



1. Survey 

2. Problems 



	 2.1 Placement

	 2.2 Routing



    



	 2.3 Logic Synthesis: Operator Optimization

	 2.4 Logic Synthesis: Operator  Sequence Scheduling



     2.5 PPA Prediction



### [Survey Papers](#content)



1. ✨**Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview**. arxiv, 22. [paper](https://arxiv.org/abs/2202.13564)



    *Junchi Yan, Xianglong Lyu, Ruoyu Cheng, Yibo Lin*



2. **Machine Learning for Electronic Design Automation: A Survey**. TODAES, 21. [journal](https://dl.acm.org/doi/abs/10.1145/3451179)



    *Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, Yu Wang*

    

3. **A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications**. TODAES, 21. [journal](https://dl.acm.org/doi/pdf/10.1145/3543853)



    *Authors: Daniela Sánchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Robert Wille, Wolfgang Ecker*



    

## [Problems](#content)



### [Placement](#content)



1. ✨**On Joint Learning for Solving Placement and Routing in Chip Design**. NeurIPS, 21. [paper](https://proceedings.neurips.cc/paper/2021/file/898aef0932f6aaecda27aba8e9903991-Paper.pdf), [code](https://github.com/Thinklab-SJTU/EDA-AI/tree/main/DeepPlace.)



    *Ruoyu Cheng, Junchi Yan*

    

2. ✨**The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design**, NeurIPS, 22. [paper](https://openreview.net/pdf?id=uNYqDfPEDD8), [code](https://github.com/Thinklab-SJTU/EDA-AI/tree/main/PRNet)



    *Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye HAO, Junchi Yan*

    

3. **Placement Optimization via PPA-Directed Graph Clustering**. MLCAD, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9900089)



    *Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing Ren*

    

4. **MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning**. NeurIPS, 22. [paper](https://openreview.net/pdf?id=T2DBbSh6_uY)



    *Yao Lai, Yao Mu, Ping Luo*



5. **A graph placement methodology for fast chip design**. Nature, 21. [paper](https://www.nature.com/articles/s41586-021-03544-w.pdf)



    *Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, Jeff Dean*

    

6. **DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement**. DAC, 19. [paper](https://dl.acm.org/doi/pdf/10.1145/3316781.3317803), [code](https://github.com/limbo018/DREAMPlace)



7. **Floorplanning with Graph Attention**. DAC, 22. [paper](https://dl.acm.org/doi/pdf/10.1145/3489517.3530484) 



    *Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang*



8. **GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning**. TCAD, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9628153)



    *Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen*



9. **GraphPlanner: Floorplanning with Graph Neural Network**. TODAES, 22. [paper](https://dl.acm.org/doi/pdf/10.1145/3555804)



    *Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang*



10. **Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model**. DATE, 19. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8715126)



    *Yu-Hung Huang, Zhiyao Xie, Guan-Qi Fang, Tao-Chun Yu, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu*



### [Routing](#content)



1. ✨**On Joint Learning for Solving Placement and Routing in Chip Design**. NeurIPS, 21. [paper](https://proceedings.neurips.cc/paper/2021/file/898aef0932f6aaecda27aba8e9903991-Paper.pdf), [code](https://github.com/Thinklab-SJTU/EDA-AI/tree/main/DeepPlace.)



    *Ruoyu Cheng, Junchi Yan*

    

2. ✨**The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design**, NeurIPS, 22. [paper](https://openreview.net/pdf?id=uNYqDfPEDD8), [code](https://github.com/Thinklab-SJTU/EDA-AI/tree/main/PRNet)



    *Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye HAO, Junchi Yan*

    

3. **A Deep Reinforcement Learning Approach for Global Routing**. Journal of Mechanical Design, 19. [paper](https://arxiv.org/pdf/1906.08809.pdf)



    *Haiguang Liao, Wentai Zhang, Xuliang Dong, Barnabas Poczos, Kenji Shimada, Levent Burak Kara*

    

4. **A Nesterov’s accelerated quasi-Newton method for global routing using deep reinforcement learning**. NOLTA, 21. [paper](https://arxiv.org/pdf/2010.09465.pdf)



    *S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai*

    

5. **Late Breaking Results: A Neural Network that Routes ICs**. DAC, 20. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9218598)



    *Dmitry Utyamishev, Inna Partin-Vaisband*



### [Logic Synthesis: Operator Sequence Scheduling](#content)



1. **PIMap: A flexible framework for improving LUT-based technology mapping via parallelized iterative optimization**. TRETS, 19. [paper](https://dl.acm.org/doi/pdf/10.1145/3268344)



    *Gai Liu, Zhiru Zhang*

    

2. **HiMap: Fast and scalable high-quality mapping on CGRA via hierarchical abstraction**. DATE, 21. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9634113&casa_token=me19az3jHwgAAAAA:EGudF-ofaEY5xahEO44VAAb_p2HDy_UOCMcKeZQpj6Ook0dLJslZOUT60KEfylYmT_vWcZMzt75M_A)



    *Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele*

    

3. **Deep learning for logic optimization algorithms**. ISCAS, 18. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8351885)



    *Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frederic Kaplan, Sabine Susstrunk, Giovanni De Micheli*



4. **DRiLLS: Deep reinforcement learning for logic synthesis**. ASP-DAC, 20. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9045559&casa_token=PIAABrGnmVkAAAAA:cXniAzWXrNOBJz8wKm1pUwTiO82wnGauCkMCJIXE8BkfOWZ7nIulIi4kSdeEJRU66euSB_XD-_L0pA), [code](https://github.com/scale-lab/DRiLLS)



    *Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda*



5. **Exploring logic optimizations with reinforcement learning and graph convolutional network**. MLCAD. 20. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9394650), [code](https://github.com/krzhu/abcRL)



    *Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan*



6. **Logic Synthesis Optimization Sequence Tuning Using RL-Based LSTM and Graph Isomorphism Network**. IEEE Trans. Circuits Syst. II Express Briefs, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9759467)



    *Chenghao Yang, Yinshui Xia, Zhufei Chu, Xiaojing Zha*



7. **BOiLS: Bayesian Optimisation for Logic Synthesis**. DATE, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9774632), [code](https://github.com/huawei-noah/HEBO/tree/master/BOiLS)



    *Antoine Grosnit, Cedric Malherbe, Rasul Tutunov, Xingchen Wan, Jun Wang, Haitham Bou-Ammar*



8. **Batch Sequential Black-box Optimization with Embedding Alignment Cells for Logic Synthesis**. ICCAD, 22.



    *Chang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, Mingxuan Yuan, Jianye Hao*

    

### [Logic Synthesis: Operator Optimization](#content)



1. **SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping**. DAC, 21.



    *Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca Amaru, Cunxi Yu, Pierre-Emmanuel Gaillardon*

    

2. **Improving LUT-based Optimization for ASICs**. DAC, 22.



    *Walter Lau Neto, Luca Amaru, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon*



### [PPA Prediction](#content)



1. **A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction**. CAD, 22. [paper](https://guozz.cn/publication/mltimerdac-22/mltimerdac-22.pdf), [code](https://github.com/TimingPredict/TimingPredict)



    *Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin*

    

2. **Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble**. ISPD, 22. [paper](https://dl.acm.org/doi/abs/10.1145/3505170.3506722)



    *Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota Authors Info & Claims*

    

3. **Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning**. ICCAD, 21. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9643435)



    *Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim*

    

4. **CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks**. VLSI-SoC, 19. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8920342)



    *Robert Kirby, Saad Godil, Rajarshi Roy, Bryan Catanzaro*

    

5. **Fast and Accurate PPA Modeling with Transfer Learning**. ICCAD, 21. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9643533)



    *W. Rhett Davis, Paul Franzon, Luis Francisco, Billy Huggins, Rajeev Jain*



6. **Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction**. ICCAD, 21. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9643446)



    *Amur Ghose, Vincent Zhang, Yingxue Zhang, Dong Li, Wulong Liu, Mark Coates*

    

7. **Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism**. DAC, 2019. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8807063)



    *Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, Jiang Hu*

    

8. **Preplacement Net Length and Timing Estimation by Customized Graph Neural Network**. TCAD, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9707500)



    *Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Chen-Chia Chang, Jingyu Pan, Yiran Chen*



9. **Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework**. ASP-DAC, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9712484). 



    *Tai Yang, Guoqing He, Peng Cao*

    

10. **Placement Optimization via PPA-Directed Graph Clustering**. MLCAD, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9900089)



    *Yi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing Ren*

    

11. **NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network**. DATE, 22. [paper](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9774525)



    *Fuping Li, Ying Wang, Cheng Liu, Huawei Li, Xiaowei Li*